MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 264

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7.8 RESET OPERATION
MOTOROLA
NOTE: The alternate bus master must sample AS high on two consecutive rising edges ofthe clock (after BGACK is recognized
low) before taking the bus.
A timing diagram of the bus arbitration sequence during a processor bus
system or the processor resets external devices. When power is applied to
the system, external circuitry should assert RESET for a minimum of 520
ven to their inactive state). Once RESET negates, all control signals are driven
to their inactive state, the data bus is in read mode, and the address bus is
cycle is shown in Figure 7-60. The bus arbitration sequence while the bus is
inactive (i.e., executing internal operations such as a multiply instruction) is
shown in Figure 7-63.
RESET is a bidirectional signal with which an external device resets the
clocks after VCC is within tolerance. Figure 7-64 is a timing diagram of the
powerup reset operation, showing the relationships between RESET, VCC,
and bus signals. The clock signal is required to be stable b y the time VCC
entire bus three-states (except for non-three-statable signals, which are dri-
driven. After this, the first bus cycle for reset exception processing begins.
reaches the minimum operating specification. During the reset period, the
ADDRESS
B G A C K
C L K _ _
A S
Figure 7-62. Single-Wire Bus Arbitration Timing Diagram
MC68030 USER'S MANUAL
I~
~ _ DO NOT
X
TAKE BUS ~
,
SEE NOTE
- -
~-TAKE BUS
r
> - -
7-103