MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 150

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
CYCLE
2
3
4
1
5
6
7
8
LONGWORD
the requested long-word spans. The first cycle requests a long word at ad-
The sequence of access for the entire operation is b6, b7, b4, b5, b8, b9, bA,
Figure 6-8 shows a misaligned access of a long word at address $06 from
an
operand requires eight read cycles, since accesses to all eight addresses
return 8-bit port-size encodings. These cycles fetch the two cache entries that
dress $06 and accepts the first requested byte (b6). The subsequent transfers
of the first long word are performed in the following order: b7, b4, b5. The
remaining four read cycles transfer the four bytes of the second cache entry.
and bB.
3-BYTE
W O R D
W O R D
W O R D
SIZE
BYTE
BYTE
BYTE
8-bit port requiring eight bus cycles to complete. Reading this long-word
ADDRESS
$06
$07
$04
$05
$08
$09
$OA
SOB
SOB
Figure 6-8. Single Entry Mode Operation - -
Misaligned Long Word and 8-Bit Port
MC68030 USER'S MANUAL
[ - ~
$04
[ ~
B
1-I-i
$08
El
- FIRST BYTE OF OPERANDLATCHED
- SECOND BYTE OF DPERAND
- TO FILL THE CACHE ENTRY ATS04
- REMAINDER OF CACHE ENTRY ATSO4
- THIRD BYTE OF OPERAND
- LAST BYTE OF DPERAND
- TO FILL CACHE ENTRY AT$08
-
$0C
REMAINDER DF ENTRY AT$08
coMMENT
6-13
6