MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 560

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
12.6.2 Instruction-Only External Cache Implementations
12.7 DEBUGGING AIDS
To minimize the potential for delays in retrying a bus cycle, the negation path
The available cache tag lookup, compare, and logic delay (D) and (E) time
for this implementation is given by Equation 12-5 of Table 12-2 (40 ns at 20.0
A further design consideration is the response of the main memory controller
to accesses that miss in the cache and are retried. During a retry operation
ously drives the address bus with the address that caused the retry to be
signaled. This presents the designer with the opportunity to utilize this in-
formation to continue (or initiate) the access in the main memory (by latching
the state of the AS signal during the initial bus cycle and holding it asserted
for the duration of the retry), thus decreasing the overhead associated with
The MC68030 supports the monitoring of internal microsequencer activity
with the STATUS and REFILL signals. The use of these signals is described
of the bus error and halt signals should be carefully controlled. Light capa-
citive loading of these signals lines as well as the use of a properly sized
pullup resistor for any open collector drivers, or some equivalent method,
is recommended.
and in the absence of arbitration for the logical bus, the MC68030 continu-
retrying the cycle.
In some cases, particularly in
ence is a concern, it is desirable to store only instruction operands since they
are not consideredto be alterable and, hence, cannot generate stale data. In
general, this is feasible with the MC68000 architecture as long as PC relative
addressing modes are not used. This restriction allows program and data
accesses to be distinguished externally by decoding the function code sig-
in the following paragraph. A useful device to aid programming debugging
is described in 12.7.2 Real-Time
MHz with no wait states).
nals.
MC68030 USER'S MANUAL
multiprocessing
Instruction Trace.
systems where cache coher-
12-35
1: