ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 85

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB On-The-Go-Dual-Role Device Controller Timing
Table 62
troller timing requirements.
Table 62. USB On-The-Go Dual-Role Device Controller Timing Requirements
JTAG Test And Emulation Port Timing
Table 63
Table 63. JTAG Port Timing
1
2
3
DCLK0-1, DCLK0–1, DCS1–0, DCLKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, CLKOUT, A3–1, and MFS.
Parameter
Timing Requirements
f
FS
Parameter
Timing Parameters
t
t
t
t
t
t
Switching Characteristics
t
t
System inputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, ATAPI_PDIAG, RESET, NMI, and
50 MHz Maximum
System outputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, DA12–0, DBA1–0, DQM1–0,
USB
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
BMODE3–0.
USB
describes the USB On-The-Go Dual-Role Device Con-
and
OUTPUTS
SYSTEM
SYSTEM
INPUTS
TMS
TDO
Figure 60
TCK
TDI
USB_XI frequency
USB_XI Clock Frequency Stability
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse-Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
describe JTAG port operations.
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
2
(measured in TCK cycles)
t
DSYS
t
DTDO
t
TCK
Rev. C | Page 85 of 100 | February 2010
t
SSYS
t
STAP
1
3
1
Figure 60. JTAG Port Timing
t
HTAP
t
HSYS
Min
9
–50
Min
20
4
4
4
11
4
0
Max
33.3
+50
Max
10
16.5
Unit
MHz
ppm
Unit
ns
ns
ns
ns
ns
t
ns
ns
TCK