ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 51

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Port Bus Request and Grant Cycle Timing
Table 35
on Page 52
operations for synchronous and for asynchronous BR.
Table 35. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
BS
BH
SD
SE
DBG
EBG
DBH
EBH
and
describe external port bus request and grant cycle
Table 36 on Page 52
BR Asserted to CLKOUT Low Setup
CLKOUT Low to BR Deasserted Hold Time
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
CLKOUT Low to BG Asserted Output Delay
CLKOUT Low to BG Deasserted Output Hold
CLKOUT Low to BGH Asserted Output Delay
CLKOUT Low to BGH Deasserted Output Hold
ADDR 19-1
CLKOUT
ABE1-0
AMSx
AWE
BGH
ARE
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
BR
BG
and
Figure 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Figure 21
t
BS
and
Rev. C | Page 51 of 100 | February 2010
Figure 22
t
t
t
SD
SD
t
t
DBH
DBG
t
BH
Min
5.0
0.0
t
t
t
t
t
SE
SE
SE
EBG
EBH
Max
5.0
5.0
4.0
4.0
3.6
3.6
Unit
ns
ns
ns
ns
ns
ns
ns
ns