ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 23

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
DEVELOPMENT TOOLS
The ADSP-BF54x Blackfin processors are supported with a
complete set of CROSSCORE® software and hardware develop-
ment tools, including Analog Devices emulators and
VisualDSP++® development environment. The same emulator
hardware that supports other Blackfin processors also fully
emulates the ADSP-BF54x Blackfin processors.
EZ-KIT Lite Evaluation Board
For evaluation of ADSP-BF54x Blackfin processors, use the
ADSP-BF548 EZ-KIT Lite
Devices. Order part number ADZS-BF548-EZLITE. The board
comes with on-chip emulation capabilities and is equipped to
enable software development. Multiple daughter cards are
available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG processor. The emulator uses
the TAP to access the internal features of the processor, allow-
ing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor is
set running at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see Analog Devices JTAG Emulation Technical Reference
• Seamlessly integrated DSP/MCU features are optimized for
• A multi-issue load/store modified-Harvard architecture,
• All registers, I/O, and memory are mapped into a unified
• Microcontroller features, such as arbitrary bit and bit-field
• Code density enhancements, which include intermixing of
both 8-bit and 16-bit operations.
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
4G byte memory space, providing a simplified program-
ming model.
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
®
board available from Analog
Rev. C | Page 23 of 100 | February 2010
(EE-68) on the Analog Devices web site under
www.analog.com/ee-notes. This document is updated regularly
to keep pace with improvements to emulator support.
MXVR BOARD LAYOUT GUIDELINES
The MXVR Loop Filter RC network is connected between the
MLF_P and MLF_M pins in the following manner:
Capacitors:
Resistor:
The RC network should be located physically close to the
MLF_P and MLF_M pins on the board.
The RC network should be shielded using GND
Avoid routing other switching signals near the RC network to
avoid crosstalk.
MXI driven with external clock oscillator IC:
MXI/MXO with external crystal:
V
DDMP
• C1: 0.047 µF (PPS type, 2% tolerance recommended)
• C2: 330 pF (PPS type, 2% tolerance recommended)
• R1: 330 Ω (1% tolerance)
• MXI should be driven with the clock output of a clock
• MXO should be left unconnected.
• Avoid routing other switching signals near the oscillator
• The crystal must be a fundamental mode crystal running at
• The crystal and load capacitors should be placed physically
• Board trace capacitance on each lead should not be more
• Trace capacitance plus load capacitance should equal the
• Avoid routing other switching signals near the crystal and
• Route V
• Drive V
• Place a ferrite bead between the V
• Locally bypass V
• Avoid routing switching signals near to V
oscillator IC running at a frequency of 49.152 MHz or
45.1584 MHz.
and clock output trace to avoid crosstalk. When not possi-
ble, shield traces with ground.
a frequency of 49.152 MHz or 45.1584 MHz.
close to the MXI and MXO pins on the board.
than 3 pF.
load capacitance specification for the crystal.
components to avoid crosstalk. When not possible, shield
traces and components with ground.
power planes.
V
capacitors to GND
traces to avoid crosstalk.
/GND
DDMP
pin for noise isolation.
MP
DDMP
DDMP
—MXVR PLL power domain:
to same level as V
and GND
DDMP
MP
.
with 0.1 µF and 0.01 µF decoupling
MP
with wide traces or as isolated
DDINT
DDINT
.
power plane and the
DDMP
MP
traces.
and GND
MP