ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 31

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12. Pin Descriptions (Continued)
Pin Name
Port J: GPIO/AMC/ATAPI
PJ0/ARDY/WAIT
PJ1/ND_CE
PJ2/ND_RB
PJ3/ATAPI_DIOR
PJ4/ATAPI_DIOW
PJ5/ATAPI_CS0
PJ6/ATAPI_CS1
PJ7/ATAPI_DMACK
PJ8/ATAPI_DMARQ
PJ9/ATAPI_INTRQ
PJ10/ATAPI_IORDY
PJ11/BR
PJ12/BG
PJ13/BGH
DDR Memory Interface
DA0–12
DBA0–1
DQ0–15
DQS0–1
DQM0–1
DCLK0–1
DCLK0–1
DCS0–1
DCLKE
DRAS
DCAS
DWE
DDR_VREF
DDR_VSSR
Asynchronous Memory Interface
A1-3
D0-15/ND_D0-15/ATAPI_D0-15
AMS0–3
ABE0 /ND_CLE
ABE1/ND_ALE
AOE/NR_ADV
ARE
AWE
ATAPI Controller Pins
ATAPI_PDIAG
9
8
6
6
7
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C | Page 31 of 100 | February 2010
I/O
I/O GPIO/ Async Ready/NOR Wait
I/O GPIO/NAND Chip Enable
I/O GPIO/NAND Ready Busy
I/O GPIO/ATAPI Read
I/O GPIO/ATAPI Write
I/O GPIO/ATAPI Chip Select/Command Block
I/O GPIO/ATAPI Chip Select
I/O GPIO/ATAPI DMA Acknowledge
I/O GPIO/ATAPI DMA Request
I/O GPIO/Interrupt Request from the Device
I/O GPIO/ATAPI Ready Handshake
I/O GPIO/Bus Request
I/O GPIO/Bus Grant
I/O GPIO/Bus Grant Hang
O
O
I/O DDR Data Bus
I/O DDR Data Strobe
O
O
O
O
O
O
O
O
I
I
O
I/O Data Bus for Async, NAND and ATAPI Accesses
O
O
O
O
O
O
I
1
Function (First/Second/Third/Fourth)
DDR Address Bus
DDR Bank Active Strobe
DDR Data Mask for Reads and Writes
DDR Output Clock
DDR Complementary Output Clock
DDR Chip Selects
DDR Clock Enable
DDR Row Address Strobe
DDR Column Address Strobe
DDR Write Enable
DDR Voltage Reference
DDR Voltage Reference Shield (Must be connected to GND.)
Address Bus for Async and ATAPI Addresses
Bank Selects (Pull high with a resistor when used as chip select.)
Byte Enables:Data Masks for Asynchronous Access/NAND Command
Latch Enable
Byte Enables:Data Masks for Asynchronous Access/NAND Address Latch
Enable
Output Enable/NOR Address Data Valid
Read Enable/NOR Output Enable
Write Enable
Determines if an 80-pin cable is connected to the host. (Pull high or low
when unused.)
Driver
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
2