ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 82

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
ATAPI Ultra DMA Data-Out Transfer Timing
Table 61
ultra DMA data-out transfer timing.
Table 61. ATAPI Ultra DMA Data-Out Transfer Timing
1
2
3
ATAPI Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
ATAPI Timing Register Setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation.
ATA/ATAPI-6 compliant functionality with limited speed.
This timing equation can be used to calculate both the minimum and maximum t
CYC
2CYC
DVS
DVH
CVS
CVH
DZFS
LI
MLI
ENV
RFS
ACK
SS
2
3
and
Cycle time
Two cycle time
Data valid setup time at sender
Data valid hold time at sender
CRC word valid setup time at host
CRC word valid hold time at host
Time from data output released-to-driving to first
strobe timing
Limited interlock time
Interlock time with minimum
ATAPI_DMACK to ATAPI_DIOR/DIOW
Ready to final strobe time
Setup and Hold time for ATAPI_DMACK
Time from STROBE edge to assertion of ATAPI_DIOW TSS
Figure 56
through
Figure 59
describes the ATAPI
Rev. C | Page 82 of 100 | February 2010
ATAPI_ULTRA_TIM_x Timing
Register Setting
TDVS, TCYC_TDVS
TDVS, TCYC_TDVS
TDVS
TCYC_TDVS
TDVS
TACK
TDVS
N/A
TMLI
TENV
N/A
TACK
ENV
.
1
Timing Equation
(TDVS + TCYC_TDVS) × t
2 × (TDVS + TCYC_TDVS) × t
TDVS × t
TMLI × t
(TENV × t
2 × t
TACK × t
TCYC_TDVS × t
TDVS × t
TACK × t
TDVS × t
2 × t
TSS × t
BD
BD
+ 2 × t
+ 2 × t
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
– (t
– (t
– (t
– (t
– (t
– (t
– (t
) +/– (t
SCLK
SCLK
SK1
SK1
SCLK
SK1
SK1
SK1
SK1
SK1
+ t
+ t
+ t
+ t
+ t
+ t
+ t
+ t
+ t
– (t
SK1
SK2
OD
OD
SK2
SK2
SK2
SK2
SK2
SK2
)
SK1
+ t
)
)
)
)
)
)
SCLK
+ t
SK2
)
SK2
SCLK
)