ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 59

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Parallel Peripheral Interface Timing
Table 40
Figure 33 on Page
enhanced parallel peripheral interface timing operations.
Table 40. Enhanced Parallel Peripheral Interface Timing
Parameter
Timing Requirements
t
t
Timing Requirements—GP Input and Frame Capture Modes
t
t
t
t
Switching Characteristics—GP Output and Frame Capture Modes
t
t
t
t
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
and
Figure 32 on Page
60, and
PPIx_CLK Width
PPIx_CLK Period
External Frame Sync Setup Before PPIx_CLK
External Frame Sync Hold After PPIx_CLK
Receive Data Setup Before PPIx_CLK
Receive Data Hold After PPIx_CLK
Internal Frame Sync Delay After PPIx_CLK
Internal Frame Sync Hold After PPIx_CLK
Transmit Data Delay After PPIx_CLK
Transmit Data Hold After PPIx_CLK
PPI_FS1/2
PPI_DATA
PPI_FS1/2
PPI_DATA
PPI_CLK
PPI_CLK
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Figure 31 on Page 59
SAMPLING EDGE
DATA DRIVING/
FRAME SYNC
60,
t
SFSPE
Figure 30 on Page
SAMPLED
Figure 30. EPPI GP Rx Mode with External Frame Sync Timing
DATA0 IS
Figure 31. EPPI GP Tx Mode with External Frame Sync Timing
describe
Rev. C | Page 59 of 100 | February 2010
59,
t
HFSPE
SAMPLING EDGE
t
DATA DRIVING/
t
t
FRAME SYNC
SFSPE
DDTPE
HDTPE
t
SDRPE
t
HFSPE
SAMPLED
DATA1 IS
t
PCLKW
t
PCLKW
t
HDRPE
t
PCLK
t
PCLK
Min
6.0
13.3
0.9
1.9
1.6
1.5
2.4
2.4
Max
10.5
9.9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns