ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 45

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 29. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
1
2
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
S = number of programmed setup cycles, RA = number of programmed read access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE.
SDAT
HDAT
DANR
HAA
DO
HO
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Negated Delay from AMSx Asserted
ARDY Asserted Hold After ARE Negated
Output Delay After CLKOUT
Output Hold After CLKOUT
DATA 15–0
ADDR19–1
CLKOUT
ABE1–0
ARDY
AMSx
AOE
ARE
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
t
DO
Figure 14. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
2 CYCLES
SETUP
2
2
t
DO
t
Rev. C | Page 45 of 100 | February 2010
DANR
PROGRAMMED READ
ACCESS 4 CYCLES
1
ACCESS EXTENDED
3 CYCLES
t
SDAT
Min
5.0
0.8
0.0
0.3
1 CYCLE
t
HO
HOLD
t
t
HDAT
HO
t
HAA
Max
(S + RA – 2) × t
6.0
SCLK
Unit
ns
ns
ns
ns
ns
ns