ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 18

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Power Domains
As shown in
port different power domains. The use of multiple power
domains maximizes flexibility while maintaining compliance
with industry standards and conventions. By isolating the inter-
nal logic of the ADSP-BF54x Blackfin processors into its own
power domain separate from the RTC and other I/O, the pro-
cessors can take advantage of dynamic power management
without affecting the RTC or other I/O devices. There are no
sequencing requirements for the various power domains.
Table 6. Power Domains
VOLTAGE REGULATION
The ADSP-BF54x Blackfin processors provide an on-chip volt-
age regulator that can generate processor core voltage levels
from an external supply (see specifications in
tions on Page
external components required to complete the power manage-
ment system. The regulator controls the internal logic voltage
levels and is programmable with the voltage regulator control
register (VR_CTL) in increments of 50 mV. This register can be
accessed using the bfrom_SysControl() function in the on-chip
ROM. To reduce standby power consumption, the internal volt-
age regulator can be programmed to remove power to the
processor core while keeping I/O power supplied. While in
hibernate state, V
still be applied, eliminating the need for external buffers. The
voltage regulator can be activated from this power-down state
by assertion of the RESET pin, which then initiates a boot
sequence. The regulator can also be disabled and bypassed at the
user’s discretion. For all 600 MHz speed grade models and all
automotive grade models, the internal voltage regulator must
not be used and V
information regarding design of the voltage regulator circuit,
see Switching Regulator Design Considerations for the ADSP-
BF533 Blackfin Processors (EE-228).
Power Domain
All internal logic, except RTC, DDR, and USB
RTC internal logic and crystal I/O
DDR external memory supply
USB internal logic and crystal I/O
Internal voltage regulator
MXVR PLL and logic
All other I/O
Table
34).
DDEXT
DDVR
Figure 6 on Page 18
6, the ADSP-BF54x Blackfin processors sup-
, V
must be tied to V
DDRTC
, V
DDDDR
shows the typical
, V
DDEXT
DDUSB
. For additional
Operating Condi-
, and V
VDD Range
V
V
V
V
V
V
V
DDINT
DDRTC
DDDDR
DDUSB
DDVR
DDMP
DDEXT
Rev. C | Page 18 of 100 | February 2010
DDVR
can
CLOCK SIGNALS
The ADSP-BF54x Blackfin processors can be clocked by an
external crystal, a sine wave input, or a buffered, shaped clock
derived from an external clock oscillator.
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF54x Blackfin processors
include an on-chip oscillator circuit, an external crystal may be
used. For fundamental frequency operation, use the circuit
shown in
microprocessor-grade crystal is connected across the CLKIN
and XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 kΩ range. Typically, further parallel
resistors are not recommended. The two capacitors and the
series resistor shown in
of the sine frequency. The 1MOhm pull-up resistor on the
XTAL pin guarantees that the clock circuit is properly held inac-
tive when the processor is in the hibernate state.
The capacitor and resistor values shown in
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. System designs should
verify the customized values based on careful investigations on
multiple devices over temperature range.
100μF
2.7V TO 3.6V
INPUT VOLTAGE
RANGE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
+
Figure
LOW ESR
10μF
100nF
7. A parallel-resonant, fundamental frequency,
Figure 6. Voltage Regulator Circuit
(LOW-INDUCTANCE)
FDS9431A
Figure 7
V
DDVR
fine-tune phase and amplitude
ZHCS1000
INDUCTANCE WIRE
SHORT AND LOW-
10μH
SET OF DECOUPLING
CAPACITORS
100μF
Figure 7
+
are typical
V
V
VR
VR
GND
DDVR
DDINT
OUT
OUT