XC4VFX12-11FFG668C Xilinx Inc, XC4VFX12-11FFG668C Datasheet - Page 374

• Manufacturer Part Number: XC4VFX12-11FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11FFG668C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
374
ISERDES Clocking Methods
IOBDELAY Attribute
NUM_CE Attribute
SERDES_MODE Attribute
The IOBDELAY attribute chooses the paths (combinatorial or registered) where the delay
through the delay element is applied. The possible values for this attribute are NONE
(default), IBUF, IFD, and BOTH.
each attribute value.
Table 8-4: IOBDELAY Attribute Value
The NUM_CE attribute defines the number of clock enables (CE1 and CE2) used. The
possible values are 1 and 2 (default = 1).
The SERDES_MODE attribute defines whether the ISERDES module is a master or slave
when using width expansion. The possible values are MASTER and SLAVE. The default
value is MASTER. See
Networking Interface Type
The phase relationship of CLK and CLKDIV is important in the serial-to-parallel
conversion process. Ideally, CLK and CLKDIV are phase-aligned. There is of course a
tolerance around the ideal phase alignment. There are several clocking arrangements
within the FPGA that are guaranteed by design to meet the phase relationship
requirements of CLK and CLKDIV (shown below). These are the only valid clocking
arrangements for the ISERDES.
•
•
•
Memory Interface Type
•
•
•
The clocking arrangement using BUFIO and BUFR is shown in
appears that BUFIO and BUFR are not phase-aligned at the inputs of the ISERDES.
However, the hardware is slightly different from the software model. In hardware, BUFIO
and BUFR are actually connected in parallel, such that the CLK and CLKDIV inputs of the
ISERDES receive phase-aligned clocks. Connecting BUFIO and BUFR in HDL as shown in
IOBDELAY
NONE
IBUF
IFD
BOTH
Value
CLK driven by BUFIO, CLKDIV driven by BUFR
CLK driven by DCM, CLKDIV driven by the CLKDV output of the same DCM
CLK driven by PMCD, CLKDIV driven by CLKA1Dx of same PMCD
CLK driven by BUFIO or BUFG
OCLK driven by DCM and CLKDIV driven by CLKDV output of same DCM
OCLK driven by PMCD and CLKDIV driven by CLKA1Dx of same PMCD
Combinatorial Output Path (O)?
Delay Element Applied on
“ISERDES Width Expansion.”
www.xilinx.com
Yes
No
Yes
No
Table 8-4
summarizes the various output paths used for
Delay Element Applied on Registered
Output Path (Q1–Q6)?
UG070 (v2.6) December 1, 2008
Figure
Virtex-4 FPGA User Guide
No
No
Yes
Yes
8-7. In the figure, it
R