XC4VFX12-11FFG668C Xilinx Inc, XC4VFX12-11FFG668C Datasheet - Page 323

• Manufacturer Part Number: XC4VFX12-11FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11FFG668C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Combinatorial Input Path
Input DDR Overview (IDDR)
R
OPPOSITE_EDGE Mode
The SRVAL attributes can be set individually for each storage element in the ILOGIC block,
but the choice of synchronous or asynchronous set/reset (SRTYPE) can not be set
individually for each storage element in the ILOGIC block.
The SR and REV pins are shared between adjacent ILOGIC/ISERDES and
OLOGIC/OSERDES.
Most of the control signals have an optional inverter. Any inverter placed on a control
signal is automatically absorbed into the ILOGIC block (i.e., no CLBs are used).
The following sections discuss the various resources within the ILOGIC blocks. All
connections between the ILOGIC resources are managed in Xilinx® software.
The combinatorial input path is used to create a direct connection from the input driver to
the FPGA logic. This path is used by software automatically when:
1.
2.
Virtex-4 devices have dedicated registers in the ILOGIC to implement input double-data-
rate (DDR) registers. This feature is used by instantiating the IDDR primitive.
There is only one clock input to the IDDR primitive. Falling edge data is clocked by a
locally inverted version of the input clock. All clocks feeding into the I/O tile are fully
multiplexed, i.e., there is no clock sharing between ILOGIC or OLOGIC blocks. The IDDR
primitive supports the following modes of operation:
•
•
•
The SAME_EDGE and SAME_EDGE_PIPELINED modes are new for the Virtex-4
architecture. These new modes allow designers to transfer falling edge data to the rising
edge domain within the ILOGIC block, saving CLB and clock resources, and increasing
performance. These modes are implemented using the DDR_CLK_EDGE attribute. The
following sections describe each of the modes in detail.
A traditional input DDR solution, or OPPOSITE_EDGE mode, is accomplished via a single
input signal driving two registers (IFF1 and IFF2) in the ILOGIC. Both registers are rising
edge triggered. The second register (IFF2) receives an inverted version of the clock. The
result is that rising edge data is presented to the fabric via the first register output (Q1) and
falling edge data via the second register output (Q2). This structure is similar to the
Virtex-II and Virtex-II Pro FPGA implementation.
There is a direct (unregistered) connection from input data to logic resources in the
FPGA logic.
The “pack I/O register/latches into IOBs” is set to OFF.
OPPOSITE_EDGE mode
SAME_EDGE mode
SAME_EDGE_PIPELINED mode
www.xilinx.com
Figure 7-2
shows a simplified input
ILOGIC Resources
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