XC4VFX12-11FFG668C Xilinx Inc, XC4VFX12-11FFG668C Datasheet - Page 331

• Manufacturer Part Number: XC4VFX12-11FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11FFG668C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Input Delay Element (IDELAY)
R
Table 7-5
in the
Table 7-5: ILOGIC Switching Characteristics
Every ILOGIC block contains a programmable absolute delay element called IDELAY.
(Refer to
element with a fixed, guaranteed tap resolution (see
to the combinatorial input path, registered input path, or both. IDELAY allows incoming
signals to be delayed on an individual basis. The delay element is calibrated to provide an
absolute delay value (T
temperature variation. Three modes of operation are available:
Setup/Hold
T
T
T
T
T
T
T
Combinatorial
T
T
Sequential Delays
T
T
T
T
T
ICE1CK
ICECK
IRSTCK
IINCCK
ISRCK
IDOCK
IDOCKD
IDI
IDID
IDLO
IDLOD
ICKQ
ICE1Q
RQ
Virtex-4 Data
Symbol
/T
/T
/T
/T
/T
/T
Figure
describes the function and control signals of the ILOGIC switching characteristics
/T
ICKSR
ICKCE
IOCKD
ICKCE1
ICKRST
ICKINC
IOCKDD
7-1,
Sheet.
“ILOGIC Block
CE1 pin setup/hold with respect to CLK
DLYCE pin setup/hold with respect to CLKDIV
DLYRST pin setup/hold with respect to CLKDIV
DLYINC pin setup/hold with respect to CLKDIV
SR/REV pin setup/hold with respect to CLK
D pin setup/hold with respect to CLK without Delay
D pin setup/hold with respect to CLK
(IOBDELAY_TYPE = DEFAULT)
D pin setup/hold with respect to CLK
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin to O pin propagation delay, no Delay
D pin to O pin propagation delay (IOBDELAY_TYPE = DEFAULT)
D pin to O pin propagation delay
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin to Q1 pin using flip-flop as a latch without Delay
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = DEFAULT)
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
CLK to Q outputs
CE1 pin to Q1 using flip-flop as a latch, propagation delay
SR/REV pin to OQ/TQ out
IDELAYRESOLUTION
www.xilinx.com
Diagram.”) IDELAY is a 64-tap wrap-around delay
) independent of process, voltage, and
Description
Virtex-4 Data
Sheet). It can be applied
ILOGIC Resources
331