XC4VFX12-11FFG668C Xilinx Inc, XC4VFX12-11FFG668C Datasheet - Page 169

• Manufacturer Part Number: XC4VFX12-11FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11FFG668C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Software Updates
Software IP Cores
The FIFO16 built-in FIFO configurations from the FIFO Generator Core incurs the same
issues described above.
Note:
of the number of bits read from and written to the FIFO.
Please review the FIFO Generator Data Sheet for more information:
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNa
vPick=PRODUCTS&sSecondaryNavPick=Intellectual+Property&key=FIFO_Generator
Starting with ISE 8.1i Service Pack 1 software, the tools automatically detect when a
synchronous FIFO16 (RDCLK and WRCLK are connected) has been inserted into a design
and issue the following warning:
To remove this warning, use the CORE Generator software FIFO solution or the
Synchronous FIFO work-around described above.
For information on what software IP cores are affected by this issue, check the following
page:
http://www.xilinx.com/ipcenter/coregen/advisories/ip_cores_impacted_by_fifo16_ar2
2462_issue.htm
When the script is used, RDCOUNT and WRCOUNT might not be an accurate representation
WARNING:PhysDesignRules:1447 - FIFO16 XLXI_1 has been found to have
both RDCLK and WRCLK input pins connected to the same source
XLXN_5_BUFGP. Under certain circumstances, the flag behavior to the
FIFO may be undeterministic. Please consult the Xilinx website for
more details.
www.xilinx.com
FIFO16 Error Condition and Work-Arounds
169