XC4VFX12-11FFG668C Xilinx Inc, XC4VFX12-11FFG668C Datasheet - Page 128

• Manufacturer Part Number: XC4VFX12-11FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11FFG668C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
128
Content Initialization - INITP_xx
Output Latches Initialization - INIT (INIT_A & INIT_B)
Output Latches Synchronous Set/Reset - SRVAL (SRVAL_A & SRVAL_B)
Table 4-4: Block RAM Initialization Attributes
INITP_xx attributes define the initial contents of the memory cells corresponding to
DIP/DOP buses (parity bits). By default these memory cells are also initialized to all zeros.
The eight initialization attributes from INITP_00 through INITP_07 represent the memory
contents of parity bits. Each INITP_xx is a 64-digit hex-encoded bit vector with a regular
INIT_xx attribute behavior. The same formula can be used to calculate the bit positions
initialized by a particular INITP_xx attribute.
The INIT (single-port) or INIT_A and INIT_B (dual-port) attributes define the output
latches values after configuration. The width of the INIT (INIT_A & INIT_B) attribute is
the port width, as shown in
default value is 0.
The SRVAL (single-port) or SRVAL_A and SRVAL_B (dual-port) attributes define output
latch values when the SSR input is asserted. The width of the SRVAL (SRVAL_A and
SRVAL_B) attribute is the port width, as shown in
encoded bit vectors, and the default value is 0. This attribute is not available when the
optional output register attribute is set.
Attribute
INIT_0E
INIT_0F
INIT_1F
INIT_2F
INIT_3F
INIT_00
INIT_01
INIT_02
INIT_10
INIT_20
INIT_30
…
…
…
..
www.xilinx.com
Table
4-5. These attributes are hex-encoded bit vectors, and the
From
12287
12543
16383
3839
4095
4351
8191
8447
255
767
511
…
…
…
…
Memory Location
Table
4-5. These attributes are hex-
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
12032
12288
16128
3584
3840
4096
7936
8192
256
512
To
…
…
…
…
0
R