XC4VFX12-11FFG668C Xilinx Inc, XC4VFX12-11FFG668C Datasheet - Page 359

• Manufacturer Part Number: XC4VFX12-11FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11FFG668C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
OLOGIC Timing Models
R
This section discusses all timing models associated with the OLOGIC block.
describes the function and control signals of the OLOGIC switching characteristics in the
Virtex-4 Data
Table 7-13: OLOGIC Switching Characteristics
Setup/Hold
T
T
T
T
T
Clock to Out
T
T
ODCK
OOCECK
OSRCK
OTCK
OTCECK
OCKQ
RQ
endmodule;
//Example ODDR instantiation
ODDR U_ODDR(
.Q(user_q),
.C(user_c),
.CE(user_ce),
.D1(user_d1),
.D2(user_d2),
.R(user_r),
.S(user_s)
);
/T
Symbol
/T
/T
parameter INIT = 1'b0;
parameter SRTYPE = "SYNC";
/T
/T
OCKT
OCKD
OCKSR
OCKTCE
OCKOCE
Sheet.
D1/D2 pins setup/hold with respect to CLK
OCE pin setup/hold with respect to CLK
SR/REV pin setup/hold with respect to CLK
T1/T2 pins setup/hold with respect to CLK
TCE pin setup/hold with respect to CLK
CLK to OQ/TQ out
SR/REV pin to OQ/TQ out
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Description
OLOGIC Resources
Table 7-13
359