XC4VFX12-11FFG668C Xilinx Inc, XC4VFX12-11FFG668C Datasheet - Page 31

• Manufacturer Part Number: XC4VFX12-11FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11FFG668C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Table 1-5
Table 1-5: BUFGCTRL Attributes
BUFG
BUFG is simply a clock buffer with one clock input and one clock output. This primitive is
based on BUFGCTRL with some pins connected to logic High or Low.
the relationship of BUFG and BUFGCTRL. A LOC constraint is available for BUFG.
The output follows the input as shown in the timing diagram in
BUFGCE and BUFGCE_1
Unlike BUFG, BUFGCE is a clock buffer with one clock input, one clock output and a clock
enable line. This primitive is based on BUFGCTRL with some pins connected to logic High
Notes:
1. Both PRESELECT attributes cannot be TRUE at the same time.
2. The LOC constraint is available.
INIT_OUT
PRESELECT_I0
PRESELECT_I1
Attribute Name
summarizes the attributes for the BUFGCTRL primitive.
BUFG(O)
I
BUFG(I)
Initializes the BUFGCTRL output to the specified
value after configuration. Sets the positive or
negative edge behavior. Sets the output level when
changing clock selection.
after configuration
after configuration
If TRUE, the BUFGCTRL output uses the I0 input
If TRUE, the BUFGCTRL output uses the I1 input
BUFG
www.xilinx.com
Figure 1-4: BUFG Timing Diagram
Figure 1-3: BUFG as BUFGCTRL
T
BCCKO_O
O
(1)
(1)
Description
.
.
GND
GND
GND
V
V
V
V
DD
DD
DD
DD
I
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Global Clocking Resources
Figure
UG070_1_03_031208
UG070_1_04_071204
Figure 1-3
1-4.
0 (default), 1
FALSE (default),
TRUE
FALSE (default),
TRUE
Possible Values
O
illustrates
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