XC4VFX12-11FFG668C Xilinx Inc, XC4VFX12-11FFG668C Datasheet - Page 27

• Manufacturer Part Number: XC4VFX12-11FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11FFG668C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Power Savings by Disabling Global Clock Buffer
Global Clock Buffers
R
The Virtex-4 FPGA clock architecture provides a straightforward means of implementing
clock gating for the purposes of powering down portions of a design.
Most designs contain several unused BUFGMUX resources. A clock can drive multiple
BUFGMUX inputs, and the BUFGMUX outputs, which will be synchronous with each
other, can be used to drive distinct regions of logic. For example, if all the logic required to
be always operating can be constrained to a few clocking regions, then one of the
BUFGMUX outputs can be used to drive those regions. Toggling the enable of the other
BUFGMUX then provides a simple means of stopping all dynamic power consumption in
those regions of logic available for power savings.
The XPower tool can be used to estimate the power savings from such an approach. The
difference can be calculated either by toggling the BUFGMUX enable or by setting the
frequency on the corresponding clock net to 0 MHz.
There are 32 global clock buffers in every Virtex-4 device. Each half of the die (top/bottom)
contains 16 global clock buffers. A global clock input can directly connect from the P-side
of the differential input pin pair to any global clock buffer input in the same half, either top
or bottom, of the device. Each differential global clock pin pair can connect to either a
differential or single-ended clock on the PCB. If using a single-ended clock, then the P-side
of the pin pair must be used because a direct connection only exists on this pin. For pin
naming conventions, refer to the
clock connected to the N-side of the differential pair results in a local route and creates
additional delay. If a single-ended clock is connected to a differential pin pair then the
other side (N-side typically) can not be used as another single-ended clock pin. However,
it can be used as a user I/O. A device with 16 global clock pins can be connected to 16
differential or 16 single-ended board clocks. A device with 32 global clock pins can be
connected to 32 clocks under these same conditions.
Global clock buffers allow various clock/signal sources to access the global clock trees and
nets. The possible sources for input to the global clock buffers include:
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•
•
•
•
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The global clock buffers can only be driven by sources in the same half of the die
(top/bottom).
All global clock buffers can drive all clock regions in Virtex-4 devices. The
primary/secondary rules from Virtex-II and Virtex-II Pro FPGAs do not apply. However,
only eight different clocks can be driven in a single clock region. A clock region (16 CLBs)
is a branch of the clock tree consisting of eight CLB rows up and eight CLB rows down. A
clock region only spans halfway across the device.
The clock buffers are designed to be configured as a synchronous or asynchronous “glitch
free” 2:1 multiplexer with two clock inputs. Virtex-4 devices have more control pins to
provide a wider range of functionality and more robust input switching. The following
Global clock inputs
Digital Clock Manager (DCM) outputs
Phase-Matched Clock Divider (PMCD) outputs
Rocket IO Multi-Gigabit Transceivers
Other global clock buffer outputs
General interconnect
www.xilinx.com
Virtex-4 Packaging and Pinout
Global Clocking Resources
Specification. A single-ended
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