XC4VFX12-11FFG668C Xilinx Inc, XC4VFX12-11FFG668C Datasheet - Page 155

• Manufacturer Part Number: XC4VFX12-11FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11FFG668C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
FIFO Verilog Template
R
//
//
//
//
//
//
//
//
// FIFO16: Virtex-4 Block RAM Asynchronous FIFO configured for 1k deep x
// 18 wide
// Virtex-4 FPGA User Guide
threshold
or 36
or "FALSE"
);
-- End of FIFO16_inst instantiation
FIFO16 #(
) FIFO16_inst (
);
// End of FIFO16_1kx18_inst instantiation
declaration
<-----Cut code below this line---->
instance
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE"
.DATA_WIDTH(36),
Verilog
RDCLK => RDCLK,
RDEN => RDEN,
RST => RST,
WRCLK => WRCLK,
WREN => WREN
.ALMOST_FULL_OFFSET(12'h000),
.ALMOST_EMPTY_OFFSET(12'h000),
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
.ALMOSTFULL(ALMOSTFULL),
.DO(DO),
.DOP(DOP),
.EMPTY(EMPTY),
.FULL(FULL),
.RDCOUNT(RDCOUNT),
.RDERR(RDERR),
.WRCOUNT(WRCOUNT),
.WRERR(WRERR),
.DI(DI),
.DIP(DIP),
.RDCLK(RDCLK),
.RDEN(RDEN),
.RST(RST),
.WRCLK(WRCLK),
.WREN(WREN)
FIFO16
code
: following instance declaration needs to be placed in
: To incorporate this function into the design, the
: the body of the design code. The instance name
: (FIFO16_1kx18_inst) and/or the port declarations
: within the parenthesis can be changed to properly
: reference and connect this function to the design.
: All inputs and outputs must be connected.
www.xilinx.com
// 1-bit almost full output flag
// 32-bit data output
// 4-bit parity data output
// 1-bit empty output flag
// 1-bit full output flag
// 12-bit read count output
// 1-bit read error output
// 12-bit write count output
// 1-bit write error
// 32-bit data input
// 4-bit partity input
// 1-bit read clock input
// 1-bit read enable input
// 1-bit reset input
// 1-bit write clock input
// 1-bit write enable input
-- 1-bit read clock input
-- 1-bit read enable input
-- 1-bit reset input
-- 1-bit write clock input
-- 1-bit write enable input
// Sets data width to 4, 9, 18,
// Sets almost full threshold
// Sets the almost empty
FIFO VHDL and Verilog Templates
155