XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 99

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain, forc-
ing the FPGAs to start synchronously. Similarly, the start-up
sequence can be paused at any stage, waiting for selected
DCMs to lock to their respective input clock signals. See
also
The start-up sequence can by synchronized to a clock
within
STARTUP_SPARTAN3E library primitive and by setting the
StartupClk bitstream generator option. The FPGA applica-
tion can optionally assert the Global Set/Reset (GSR) and
Global
STARTUP_SPARTAN3E primitive.
Readback
Using Slave Parallel mode, configuration data from the
FPGA can be read back. Readback is supported only in the
Slave Parallel and JTAG modes.
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options
92
ConfigRate
StartupClk
UnusedPin
DONE_cycle
Option Name
Stabilizing DCM Clocks Before User Mode, page
Three-State
the
Pins/Function
Configuration,
Configuration
Configuration
FPGA
Unused I/O
DONE pin,
Affected
Startup
Startup
CCLK,
Pins
signal
application
(GTS)
Pulldown
1, 2, 3, 4 ,
( default )
Pullnone
UserClk
Values
12, 25
Pullup
Cclk
3, 6 ,
Jtag
5, 6
signals
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency and the new setting is loaded as part of the configuration bitstream. The
software default value is 6 (~6 MHz).
Default. The CCLK signal (internally or externally generated) controls the startup
sequence when the FPGA transitions from configuration mode to the user mode. See
Start-Up, page
A clock signal from within the FPGA application controls the startup sequence when
the FPGA transitions from configuration mode to the user mode. See
page
STARTUP_SPARTAN3E primitive.
The JTAG TCK input controls the startup sequence when the FPGA transitions from
configuration mode to the user mode. See
Default. All unused I/O pins have a pull-down resistor to GND.
All unused I/O pins have a pull-up resistor to the VCCO_# supply for its associated I/O
bank.
All unused I/O pins are left floating (Hi-Z, high-impedance, three-state). Use external
pull-up or pull-down resistors or logic to apply a valid signal level.
Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
Start-Up, page
using
91. The FPGA application supplies the user clock on the CLK pin on the
via
www.xilinx.com
48.
the
the
91.
91.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed RAM, and block
RAM resources. This capability is used for real-time debug-
ging.
To synchronously control when registers values are cap-
tured for readback, using the CAPTURE_SPARTAN3 library
primitive, which applies for both Spartan-3 and Spartan-3E
FPGA families.
Bitstream Generator (BitGen) Options
Various Spartan-3E FPGA functions are controlled by spe-
cific bits in the configuration bitstream image. These values
are specified when creating the bitstream image with the
Bitstream Generator (BitGen) software.
Table 57
FPGAs.
provides a list of all BitGen options for Spartan-3E
Description
Start-Up, page
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
91.
Start-Up,
R