XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 125

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pinout Descriptions
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx website at the specified location in
Table
Table 4: Xilinx Package Mechanical Drawings
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in
Table 5: Power and Ground Supply Pins by Package
4
VQ100 / VQG100
CP132 / CPG132
TQ144 / TQG144
PQ208 / PQG208
FT256 / FTG256
FG320 / FGG320
FG400 / FGG400
FG484 / FGG484
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
Package
4.
Package
VCCINT
16
16
4
6
4
4
8
8
VCCAUX
10
http://www.xilinx.com/bvdocs/packages/vq100.pdf
http://www.xilinx.com/bvdocs/packages/cp132.pdf
http://www.xilinx.com/bvdocs/packages/tq144.pdf
http://www.xilinx.com/bvdocs/packages/pq208.pdf
http://www.xilinx.com/bvdocs/packages/ft256.pdf
http://www.xilinx.com/bvdocs/packages/fg320.pdf
http://www.xilinx.com/bvdocs/packages/fg400.pdf
http://www.xilinx.com/bvdocs/packages/fg484.pdf
4
4
4
8
8
8
8
VCCO
12
16
20
24
28
8
8
9
Table
5.
GND
12
16
13
20
28
28
42
48
www.xilinx.com
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in
mum number of single-ended I/O pins available, assuming
that all I/O-, INPUT-, DUAL-, VREF-, and GCLK-type pins
are used as general-purpose I/O. Likewise, the table shows
the maximum number of differential pin-pairs available on
the package. Finally, the table shows how the total maxi-
mum user-I/Os are distributed by pin type, including the
number of unconnected—i.e., N.C.—pins on the device.
Web Link (URL)
Table
6. The table shows the maxi-
Advance Product Specification
DS312-4 (v1.1) March 21, 2005
R