EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 190
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Model
5–54
Stratix II Device Handbook, Volume 1
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL
Class I
Table 5–73. Stratix II I/O Input Delay for Column Pins (Part 1 of 3)
I/O Standard
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
P I
P C O U T
P I
P C O U T
P I
P C O U T
P I
P C O U T
P I
P C O U T
P I
P C O U T
P I
P C O U T
P I
P C O U T
P I
P C O U T
P I
P C O U T
I/O Delays
See
t
t
t
t
D I P
O P
P C O U T
P I
Table 5–72. I/O Delay Parameters
Symbol
Industrial
Tables 5–72
674
408
684
418
747
481
749
483
674
408
507
241
507
241
543
277
543
277
560
294
Minimum Timing
Delay from I/O datain to output pad
Delay from I/O output register to output pad
Delay from input pad to I/O dataout to core
Delay from input pad to I/O input register
Commercial
through
707
428
717
438
783
504
786
507
707
428
530
251
530
251
569
290
569
290
587
308
5–76
-3 Speed
Grade
for I/O delays.
1223
1210
1366
1436
1000
1223
787
774
930
787
818
382
818
382
898
462
898
462
993
557
(2)
Parameter
-3 Speed
Grade
1282
1269
1433
1506
1049
1282
1041
825
812
976
825
857
400
857
400
941
484
941
484
584
(3)
-4 Speed
Grade
1405
1390
1570
1069
1650
1149
1405
1031
1031
1141
904
889
904
939
438
939
438
530
530
640
Altera Corporation
-5 Speed
Grade
1637
1054
1619
1036
1829
1246
1922
1339
1637
1054
1094
1094
1201
1201
1329
511
511
618
618
746
April 2011
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps