EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 108
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
High-Speed Differential I/O with DPA Support
Figure 2–58. Stratix II Transmitter Channel
2–100
Stratix II Device Handbook, Volume 1
refclk
Fast
PLL
Dedicated Circuitry with DPA Support
Stratix II devices support source-synchronous interfacing with LVDS or
HyperTransport signaling at up to 1 Gbps. Stratix II devices can transmit
or receive serial channels along with a low-speed or high-speed clock.
The receiving device PLL multiplies the clock by an integer factor W = 1
through 32. For example, a HyperTransport technology application
where the data rate is 1,000 Mbps and the clock rate is 500 MHz would
require that W be set to 2. The SERDES factor J determines the parallel
data width to deserialize from receivers or to serialize for transmitters.
The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to
equal the PLL clock-multiplication W value. A design using the dynamic
phase aligner also supports all of these J factor values. For a J factor of 1,
the Stratix II device bypasses the SERDES block. For a J factor of 2, the
Stratix II device bypasses the SERDES block, and the DDR input and
output registers are used in the IOE.
of the Stratix II transmitter channel.
Each Stratix II receiver channel features a DPA block for phase detection
and selection, a SERDES, a synchronizer, and a data realigner circuit. You
can bypass the dynamic phase aligner without affecting the basic source-
synchronous operation of the channel. In addition, you can dynamically
switch between using the DPA block or bypassing the block via a control
signal from the logic array.
Stratix II receiver channel.
Data from R4, R24, C4, or
direct link interconnect
Interconnect
Local
diffioclk
load_en
10
10
Figure 2–59
Figure 2–58
shows the block diagram of the
Dedicated
Transmitter
Interface
+
–
shows the block diagram
Regional or
global clock
Up to 1 Gbps
Altera Corporation
May 2007