EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 232
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
JTAG Timing Specifications
JTAG Timing
Specifications
Figure 5–10. Stratix II JTAG Waveforms
5–96
Stratix II Device Handbook, Volume 1
TMS
TDO
TCK
TDI
t
JCH
t
Figure 5–10
JPZX
Notes to
(1)
(2)
(3)
Notes to
(1)
(2)
t
O U T H A L F J I T T E R
Table 5–100. DQS Phase Offset Delay Per Stage
Table 5–101. DDIO Outputs Half-Period Jitter
t
JCP
The delay settings are linear.
The valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to
+31 for frequency modes 1, 2, and 3.
The typical value equals the average of the minimum and maximum values.
The worst-case half period is equal to the ideal half period subtracted by the DCD
and half-period jitter values.
The half-period jitter was characterized using a PLL driving DDIO outputs.
Name
t
JCL
Speed Grade
Table
Table
shows the timing requirements for the JTAG signals.
-3
-4
-5
5–100:
5–101:
t
Half-period jitter (PLL driving DDIO outputs)
JPCO
t
JPSU
Description
Min
9
9
9
t
JPH
t
JPXZ
Notes
Max
14
14
15
Notes
(1),
Altera Corporation
(1), (2),
(2)
Max
200
April 2011
(3)
Unit
ps
ps
ps
Unit
ps