EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 218
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Duty Cycle Distortion
5–82
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS/ HyperTransport
technology
Table 5–82. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3
Devices
Row DDIO Output I/O
The information in
The DCD specification is based on a no logic array noise condition.
Standard
Table
Notes
5–82:
(1),
Table 5–82
(2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port
3.3 & 2.5 V
260
210
195
150
255
175
170
155
150
150
180
Here is an example for calculating the DCD in percentage for a DDIO
output on a row I/O on a -3 device:
If the input I/O standard is SSTL-2 and the DDIO output I/O standard is
SSTL-2 Class II, the maximum DCD is 60 ps (see
frequency is 267 MHz, the clock period T is:
Calculate the DCD as a percentage:
assumes the input clock has zero DCD.
TTL/CMOS
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
boundary)
boundary)
(T/2 – DCD) / T = (3745ps/2 – 60ps) / 3745ps = 48.4% (for low
(T/2 + DCD) / T = (3745 ps/2 + 60 ps) / 3745ps = 51.6% (for high
1.8 & 1.5 V
380
330
315
265
370
295
290
275
270
270
180
(No PLL in Clock Path)
SSTL-2
2.5 V
145
100
140
180
85
85
65
60
55
60
55
1.8 & 1.5 V
SSTL/HSTL
145
100
140
180
85
85
65
60
50
60
55
Table
HyperTransport
Technology
LVDS/
3.3 V
Altera Corporation
110
120
105
180
5–82). If the clock
65
75
75
95
90
70
90
April 2011
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps