EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 115
![IC STRATIX II FPGA 30K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
IEEE Std. 1149.1
JTAG Boundary-
Scan Support
Altera Corporation
May 2007
SII51003-4.2
All Stratix
boundary-scan test (BST) circuitry that complies with the IEEE
Std. 1149.1. JTAG boundary-scan testing can be performed either before
or after, but not during configuration. Stratix II devices can also use the
JTAG port for configuration with the Quartus
using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
Stratix II devices support IOE I/O standard setting reconfiguration
through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode through the CONFIG_IO instruction. You can use this capability
for JTAG testing before configuration when some of the Stratix II pins
drive or receive from other devices on the board using voltage-referenced
standards. Because the Stratix II device may not be configured before
JTAG testing, the I/O pins may not be configured for appropriate
electrical standards for chip-to-chip communication. Programming those
I/O standards via JTAG allows you to fully test I/O connections to other
devices.
A device operating in JTAG mode uses four required pins, TDI,TDO, TMS,
and TCK, and one optional pin, TRST. The TCK pin has an internal weak
pull-down resistor, while the TDI,TMS and
pull-ups. The JTAG input pins are powered by the 3.3-V VCCPD pins. The
TDO output pin is powered by the V
Stratix II devices also use the JTAG port to monitor the logic operation of
the device with the SignalTap
devices support the JTAG instructions shown in
1
The Stratix II device instruction register length is 10 bits and the
USERCODE register length is 32 bits.
boundary-scan register length and device IDCODE information for
Stratix II devices.
Stratix II, Stratix, Cyclone
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II, Stratix,
Cyclone II, or Cyclone devices are in the 18th of further position,
they fail configuration. This does not affect SignalTap II.
®
II devices provide Joint Test Action Group (JTAG)
3. Configuration & Testing
®
II embedded logic analyzer. Stratix II
®
Tables 3–2
II, and Cyclone devices must be
CCIO
power supply of bank 4.
TRST
®
and
II software or hardware
pins have weak internal
Table
3–3
3–1.
show the
3–1