EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 224
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
High-Speed I/O Specifications
5–88
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
f
f
TCCS
SW
Output jitter
Output t
Output t
t
DPA run length
DPA jitter tolerance
DPA lock time
H S D R
H S D R D PA
DUTY
Table 5–89. High-Speed I/O Specifications for -3 Speed Grade (Part 2 of 2)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
(data rate)
R I S E
FA L L
Table
Symbol
(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
5–89:
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
All differential standards
All differential standards
All differential I/O standards
All differential I/O standards
Data channel peak-to-peak jitter
SPI-4
Parallel Rapid I/O
Miscellaneous
Standard
Conditions
0000000000
1111111111
00001111
10010000
10101010
01010101
Training
Pattern
Transition
Density
100%
10%
25%
50%
0.44
Min
150
150
256
256
256
256
256
330
(4)
(4)
45
-3 Speed Grade
-
Notes
Typ
50
(1),
Altera Corporation
1,040
1,040
6,400
Max
760
500
200
190
160
180
55
(2)
-
Number of
repetitions
April 2011
Mbps
Mbps
Mbps
Mbps
Unit
ps
ps
ps
ps
ps
UI
UI
%