EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 233
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Document
Revision History
Altera Corporation
April 2011
April 2011, v4.5
July 2009, v4.4
May 2007, v4.3
Table 5–103. Document Revision History (Part 1 of 3)
Document
Date and
Version
Updated
Updated
●
●
●
Moved the Document Revision History section to the
end of the chapter.
Updated R
Updated f
Updated f
Table
Table
Table 5–102
devices.
Table 5–103
Note to
(1)
t
t
t
t
t
t
t
t
Symbol
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
Table 5–102. Stratix II JTAG Timing Parameters & Values
IN
IN
CONF
5–3.
5–92.
(min) in Table 5–92.
and f
A 1 ns adder is required for each V
example,
1.8 V.
in Table 5–4.
Changes Made
Table
INPFD
TCK
TCK
TCK
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
shows the JTAG timing parameters and values for Stratix II
shows the revision history for this chapter.
t
5–102:
in Table 5–93.
JPCO
clock period
clock high time
clock low time
= 12 ns if V
Parameter
C C I O
of the TDO I/O bank = 2.5 V, or 13 ns if it equals
C C I O
Stratix II Device Handbook, Volume 1
voltage step down from 3.3 V. For
Added operating junction temperature
for military use.
Updated the spread spectrum
modulation frequency (f
(100 kHz–500 kHz) to
(30 kHz–150 kHz).
DC & Switching Characteristics
Summary of Changes
Min
13
13
30
3
5
—
—
11
14
14
Max
(1)
(1)
(1)
S S
) from
Unit
ns
ns
ns
ns
ns
ns
ns
ns
5–97