EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 77
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–45. Stratix II Device Fast PLL
Notes to
(1)
(2)
(3)
(4)
(5)
I/O Structure
Altera Corporation
May 2007
Clock
Input
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES circuitry. Stratix II
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a differential I/O SERDES control signal.
Stratix II fast PLLs only support manual clock switchover.
If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
Figure
Global or
regional clock (1)
Global or
regional clock (1)
4
2–45:
f
Shaded Portions of the
PLL are Reconfigurable
Circuitry (4)
Switchover
Clock
Fast PLLs
Stratix II devices contain up to eight fast PLLs with high-speed serial
interfacing ability.
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of
the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information on enhanced and fast PLLs. See
Differential I/O with DPA Support” on page 2–96
on high-speed differential I/O support.
The Stratix II IOEs provide many features, including:
■
■
■
■
■
■
■
■
÷n
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
On-chip driver series termination
On-chip parallel termination
On-chip termination for differential standards
Programmable pull-up during configuration
Frequency
Detector
Phase
PFD
Notes
Charge
(1), (2),
Pump
Figure 2–45
Filter
Loop
(3)
÷m
shows a diagram of the fast PLL.
VCO
VCO Phase Selection
Selectable at each PLL
Output Port
Stratix II Device Handbook, Volume 1
÷k
(5)
8
Post-Scale
“High-Speed
for more information
Counters
÷c0
÷c1
÷c2
÷c3
Stratix II Architecture
4
4
8
8
2–69
diffioclk0
load_en0
load_en1
diffioclk1
Global clocks
Regional clocks
to DPA block
(2)
(3)
(3)
(2)