EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 210
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Model
5–74
Stratix II Device Handbook, Volume 1
1.8-V
LVTTL/LVCMOS
1.5-V
LVTTL/LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 2 of 5)
I/O Standard
Strength
10 mA
12 mA
12 mA
16 mA
20 mA
24 mA
10 mA
12 mA
16 mA
18 mA
20 mA
12 mA
16 mA
20 mA
24 mA
Drive
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
8 mA
4 mA
6 mA
8 mA
8 mA
8 mA
951
405
261
223
194
174
652
333
182
135
364
163
118
458
305
225
167
129
173
150
120
109
364
163
118
99
91
99
91
-3
Column I/O Pins
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
1421
516
325
274
236
209
963
347
247
194
680
207
147
122
116
570
380
282
220
175
206
160
130
127
680
207
147
122
116
-4
1421
516
325
274
236
209
963
347
247
194
680
207
147
122
116
570
380
282
220
175
206
160
130
127
680
207
147
122
116
-5
951
405
261
223
652
333
364
163
118
458
305
225
167
364
163
118
-3
-
-
-
-
-
-
-
-
-
-
-
-
-
Row I/O Pins
1421
516
325
274
963
347
680
207
147
570
380
282
220
680
207
147
-4
-
-
-
-
-
-
-
-
-
-
-
-
-
1421
516
325
274
963
347
680
207
147
570
380
282
220
680
207
147
-5
-
-
-
-
-
-
-
-
-
-
-
-
-
Dedicated Clock Outputs
904
393
253
224
199
180
618
270
198
155
350
188
505
336
248
190
148
155
140
110
350
188
94
87
85
94
94
87
85
-3
Altera Corporation
1421
516
325
274
236
209
963
347
247
194
680
207
147
122
116
570
380
282
220
175
206
160
130
127
680
207
147
122
116
-4
April 2011
1421
516
325
274
236
209
963
347
247
194
680
207
147
122
116
570
380
282
220
175
206
160
130
127
680
207
147
122
116
-5