AD9775BSVRL Analog Devices Inc, AD9775BSVRL Datasheet - Page 3

• Manufacturer Part Number: AD9775BSVRL
• Description: IC DAC 14BIT DUAL 160MSPS 80TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9775BSVRL

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• For Use With: AD9775-EBZ - BOARD EVALUATION FOR AD9775

REVISION HISTORY
12/06—Rev. D to Rev. E
Changes to Figure 52, Figure 54, Figure 55, and Figure 56 .......29
1/06—Rev. C to Rev. D
Updated Formatting..........................................................Universal
Changes to Figure 32 .................................................................... 22
Changes to Figure 108 .................................................................. 55
Updated Outline Dimensions...................................................... 58
Changes to Ordering Guide......................................................... 58
6/04—Rev. B to Rev. C
Updated Layout .................................................................Universal
Changes to DC Specifications ....................................................... 5
Changes to Absolute Maximum Ratings...................................... 9
Changes to the DAC Operation Section .................................... 25
Inserted Figure 38.......................................................................... 25
Changes to Figure 40 .................................................................... 26
Changes to Table 11 ...................................................................... 28
Changes to Programmable PLL Section..................................... 28
Changes to Figures 49, 50, and 51............................................... 29
Changes to the PLL Enabled, One-Port Mode Section............ 30
Changes to the PLL Disabled, One-Port Mode Section........... 31
Changes to the Ordering Guide .................................................. 57
Updated Outline Dimensions...................................................... 57
3/03—Rev. A to Rev. B
Changes to Register Description—Address 04h ....................... 16
Changes to Equation 1.................................................................. 16
Changes to Figure 8....................................................................... 20
Rev. E | Page 3 of 56
2/03—Rev. 0 to Rev. A
Edits to Features ...............................................................................1
Edits to DC Specifications ..............................................................3
Edits to Dynamic Specifications ....................................................4
Edits to Pin Function Descriptions ...............................................8
Edits to Table I ............................................................................... 14
Edits to Register Description—Address 02h ............................. 15
Edits to Register Description—Address 03h ............................. 16
Edits to Register Description—Address 07h, 0Bh.................... 16
Edits to Equation 1........................................................................ 16
Edits to MSB/LSB Transfers......................................................... 18
Edits to Programmable PLL......................................................... 21
Added New Figure 14 ................................................................... 22
Renumbered Figures 15–69 ......................................................... 22
Added Two-Port Data Input Mode Section............................... 23
Edits to PLL Enabled, Two-Port Mode ...................................... 24
Edits to Figure 19 .......................................................................... 24
Edits to Figure 21 .......................................................................... 25
Edits to PLL Disabled, Two-Port Mode ..................................... 25
Edits to Figure 22 .......................................................................... 25
Edits to Figure 23 .......................................................................... 26
Edits to Figure 26a ........................................................................ 27
Edits to Complex Modulation and Image Rejection of Baseband
Signals ............................................................................................. 31
Edits to Evaluation Board ............................................................ 39
Edits to Figures 56–59 .................................................................. 40
Replaced Figures 60–69................................................................ 42
Updated Outline Dimensions...................................................... 49
AD9775