AD9775BSVRL Analog Devices Inc, AD9775BSVRL Datasheet - Page 26

• Manufacturer Part Number: AD9775BSVRL
• Description: IC DAC 14BIT DUAL 160MSPS 80TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9775BSVRL

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• For Use With: AD9775-EBZ - BOARD EVALUATION FOR AD9775

AD9775
A transformer, such as the T1-1T from Mini-Circuits®, can also
be used to convert a single-ended clock to differential. This
method is used on the AD9775 evaluation board so that an external
sine wave with no dc offset can be used as a differential clock.
PECL/ECL drivers require varying termination networks,
the details of which are left out of Figure 43 and Figure 44 but
can be found in application notes such as AND8020/D from
ON Semiconductor®. These networks depend on the assumed
transmission line impedance and power supply voltage of the
clock driver.
Optimum performance of the AD9775 is achieved when the
driver is placed very close to the AD9775 clock inputs, thereby
negating any transmission line effects such as reflections due to
mismatch.
The quality of the clock and data input signals is important in
achieving optimum performance. The external clock driver
circuitry should provide the AD9775 with a low jitter clock
input that meets the minimum/maximum logic levels while
providing fast edges. Although fast clock edges help minimize
any jitter that manifests itself as phase noise on a reconstructed
waveform, the high gain bandwidth product of the AD9775
clock input comparator can tolerate differential sine wave
inputs as low as 0.5 V p-p with minimal degradation of the
output noise floor.
PROGRAMMABLE PLL
CLKIN can function either as an input data rate clock (PLL
enabled) or as a DAC data rate clock (PLL disabled) according
to the state of Address 0x02, Bit 7 in the SPI port register. The
internal operation of the AD9775 clock circuitry in these two
modes is illustrated in Figure 45 and Figure 46.
The PLL clock multiplier and distribution circuitry produce the
necessary internal synchronized 1×, 2×, 4×, and 8× clocks for
the rising edge triggered latches, interpolation filters,
modulators, and DACs. This circuitry consists of a phase
detector, charge pump, voltage controlled oscillator (VCO),
prescaler, clock distribution, and SPI port control.
The charge pump, VCO, differential clock input buffer, phase
detector, prescaler, and clock distribution are all powered from
CLKVDD. PLL lock status is indicated by the logic signal at the
DATACLK_PLL_LOCK pin, as well as by the status of Bit 1,
Register 0x00. To ensure optimum phase noise performance
from the PLL clock multiplier and distribution, CLKVDD
should originate from a clean analog supply. Table 18 defines
the minimum input data rates vs. the interpolation and PLL
divider setting. If the input data rate drops below the defined
minimum under these conditions, VCO noise may increase
significantly. The VCO speed is a function of the input data
rate, the interpolation rate, and the VCO prescaler, according to
the following function:
VCO Speed (MHz) =
Input Data Rate (MHz) × Interpolation Rate × Prescaler
Rev. E | Page 26 of 56
LATCHES
INTERPOLATION
LATCHES
Table 18. PLL Optimization
Interpolation
Rate
1
1
1
1
2
2
2
2
4
4
4
4
8
8
8
8
INTERPOLATION
CONTROL
INPUT
CONTROL
INPUT
DATA
DATA
RATE
RATE
1
1
Figure 46. PLL and Clock Circuitry with PLL Disabled
Figure 45. PLL and Clock Circuitry with PLL Enabled
2
2
0 = NO LOCK
0 = NO LOCK
PLL_LOCK
PLL_LOCK
DISTRIBUTION
DISTRIBUTION
INTERPOLATION
INTERPOLATION
1 = LOCK
MODULATORS,
INTERNAL SPI
1 = LOCK
MODULATORS,
INTERNAL SPI
CIRCUITRY
CIRCUITRY
SPI PORT
REGISTERS
REGISTERS
SPI PORT
4
4
AND DACS
CONTROL
AND DACS
CONTROL
CLOCK
CLOCK
FILTERS,
FILTERS,
Divider
Setting
1
2
4
8
1
2
4
8
1
2
4
8
1
2
4
8
8
8
CLK+
CLK+
MODULATION
MODULATION
CONTROL
CONTROL
RATE
RATE
CLK–
CLK–
PRESCALER
DETECTOR
PRESCALER
DETECTOR
Minimum
f
32
16
8
4
24
12
6
3
24
12
6
3
24
12
6
3
DATA
PHASE
PHASE
AD9775
CONTROL
CONTROL
(PLL ON)
(PLL ON)
(PRESCALER)
(PRESCALER)
AD9775
PLL DIVIDER
PLL DIVIDER
PLL
PLL
CONTROL
CONTROL
CHARGE
CHARGE
PUMP
PUMP
VCO
VCO
PLLVDD
Maximum
f
160
160
112
56
160
112
56
28
100
56
28
14
50
28
14
7
DATA
LPF