AD9775BSVRL Analog Devices Inc, AD9775BSVRL Datasheet
AD9775BSVRL
Specifications of AD9775BSVRL
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AD9775BSVRL Summary of contents
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FEATURES 14-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment f / digital quadrature modulation capability S S Direct IF transmission mode for 70 MHz + IFs Enables image ...
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AD9775 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Product Highlights ....................................................................... 4 Specifications..................................................................................... 5 DC Specifications ......................................................................... 5 Dynamic Specifications ............................................................... 6 Digital Specifications ................................................................... 7 ...
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REVISION HISTORY 12/06—Rev Rev. E Changes to Figure 52, Figure 54, Figure 55, and Figure 56 .......29 1/06—Rev Rev. D Updated Formatting..........................................................Universal Changes to Figure 32 .................................................................... 22 Changes to Figure 108 .................................................................. 55 Updated Outline ...
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AD9775 GENERAL DESCRIPTION 1 The AD9775 is the 14-bit member of the AD977x pin- compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC Accuracy Integral Nonlinearity Differential Nonlinearity ANALOG OUTPUT (for ...
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DYNAMIC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = MIN MAX transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum ...
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DIGITAL SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 MIN MAX Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic ...
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AD9775 DIGITAL FILTER SPECIFICATIONS Table 4. Half-Band Filter No. 1 (43 Coefficients) Tap Coefficient − −134 ...
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ABSOLUTE MAXIMUM RATINGS Table 7. Parameter AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD AGND, DGND, CLKGND REFIO, FSADJ1/FSADJ2 OUTA OUTB P1B13 to P1B0, P2B13 to P2B0, RESET DATACLK, PLL_LOCK CLK+, CLK– LPF SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO Junction Temperature ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLKVDD LPF CLKVDD CLKGND CLK+ CLK– CLKGND DATACLK/PLL_LOCK DGND DVDD P1B13 (MSB) P1B12 P1B11 P1B10 P1B9 P1B8 DGND DVDD P1B7 P1B6 CONNECT ...
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Table 9. Pin Function Descriptions Pin No. Mnemonic 1, 3 CLKVDD 2 LPF 4, 7 CLKGND 5 CLK+ 6 CLK− 8 DATACLK/PLL_LOCK 9, 17, 25, 35, 44, 52 DGND 10, 18, 26, 36, 43, 51 DVDD 11 to 16, 19 ...
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AD9775 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3 Ω doubly terminated, unless otherwise noted –10 –20 –30 –40 –50 –60 –70 –80 – ...
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FREQUENCY (MHz) Figure 12. Single-Tone Spectrum @ f = 160 MSPS with f DATA 90 –6dBFS 0dBFS –12dBFS ...
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AD9775 90 8 × × 2 × × FREQUENCY (MHz) Figure 18. Third-Order IMD Products vs. f OUT 1× 160 MSPS, 2× f ...
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FREQUENCY (MHz) Figure 24. Single-Tone Spurious Performance 150 MSPS, No Interpolation DATA 0 –20 –40 –60 –80 –100 FREQUENCY ...
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AD9775 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 100 200 FREQUENCY (MHz) Figure 30. Single-Tone Spurious Performance MSPS, Interpolation = 8× DATA 0 –20 –40 –60 –80 –100 –120 300 400 ...
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TERMINOLOGY Adjacent Channel Power Ratio (ACPR) A ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These ...
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MODE CONTROL (VIA SPI PORT) 1 Table 10. Mode Control via SPI Port Address Bit 7 Bit 6 0x00 SDIO LSB, MSB Bidirectional First MSB 0 = Input 1 = LSB Filter Filter ...
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REGISTER DESCRIPTIONS ADDRESS 0x00 Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an input during the data transfer (Phase 2) of the communications cycle. When set to 1, SPI_SDIO can act as an input or output, ...
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AD9775 ADDRESS 0x03 Bit 7: Allows the data rate clock (divided down from the DAC clock output at either the DATACLK/PLL_LOCK pin (Pin the SPI_SDO pin (Pin 53). The default this register ...
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FUNCTIONAL DESCRIPTION The AD9775 dual interpolating DAC consists of two data channels that can be operated independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9775 capable ...
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AD9775 INSTRUCTION BYTE The instruction byte contains the information shown next Table 16 R/W Bit 7 of the instruction byte determines whether a read or a write data transfer occurs ...
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INSTRUCTION CYCLE CS SCLK SDIO R (N) (N) SDO INSTRUCTION CYCLE CS SCLK SDIO SDO SCLK t DS INSTRUCTION BIT 7 SDIO CS SCLK SDIO SDO ...
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AD9775 DAC OPERATION The dual, 14-bit DAC output of the AD9775, along with the reference circuitry, gain, and offset registers, is shown in Figure 37. Note that an external reference can be used by simply overdriving the internal reference with ...
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The offset control defines a small current that can be added (not both) on the IDAC and QDAC. The selection OUTA OUTB of which I this offset current is directed toward is programmable OUT via Register ...
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AD9775 A transformer, such as the T1-1T from Mini-Circuits®, can also be used to convert a single-ended clock to differential. This method is used on the AD9775 evaluation board so that an external sine wave with no dc offset can ...
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In addition, if the zero-stuffing option is enabled, the VCO doubles its speed again. Phase noise may be slightly higher with the PLL enabled. Figure 47 illustrates typical phase noise perform- ance of the AD9775 with 2× interpolation and various ...
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AD9775 35 8 × × 100 f (MHz) DATA Figure 51 I vs. f vs. Interpolation Rate, PLL Disabled CLKVDD DATA SLEEP/POWER-DOWN MODES (Control Register 0x00, Bit 3 and Bit ...
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DATACLK INVERSION (Control Register 0x02, Bit 4) By programming this bit, the DATACLK signal shown in Figure 52 can be inverted. With inversion enabled, t the time between the rising edge of CLKIN and the falling edge of DATACLK. No ...
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AD9775 ONEPORTCLK DRIVER STRENGTH The drive capability of ONEPORTCLK is identical to that of DATACLK in the two-port mode. Refer to Figure 53 for performance under load conditions. IQ PAIRING (Control Register 0x02, Bit 0) In one-port mode, the interleaved ...
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It is possible to invert the I and Q selection by setting control Register 0x02, Bit 1 to the invert state (Logic 1). Figure 56 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note ...
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AD9775 MODULATION, NO INTERPOLATION With Control Register 0x01, Bit 7 and Bit 6 set to 00, the interpolation function on the AD9775 is disabled. Figure 59 through Figure 62 show the DAC output spectral characteristics of the AD9775 in the ...
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MODULATION, INTERPOLATION = 2× With Control Register 0x01, Bit 7 and Bit 6 set to 01, the interpolation rate of the AD9775 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, ...
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AD9775 MODULATION, INTERPOLATION = 4× With Control Register 0x01, Bit 7 and Bit 6 set to 10, the interpolation rate of the AD9775 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence ...
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MODULATION, INTERPOLATION = 8× With Control Register 0x01, Bit 7 and Bit 6 set to 11, the interpolation rate of the AD9775 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, ...
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AD9775 ZERO STUFFING (Control Register 0x01, Bit 3) As shown in Figure 75 null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (f is ...
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COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS In traditional transmit applications, a two-step upconversion is done in which a baseband signal is modulated by one carrier to an intermediate frequency (IF) and then modulated a second time to the ...
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IMAGE REJECTION AND SIDEBAND SUPPRESSION OF MODULATED CARRIERS As shown in Figure 79, image rejection can be achieved by applying baseband data to the AD9775 and following the AD9775 with a quadrature modulator. To process multiple carriers while still maintaining ...
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The complex carrier synthesized in the AD9775 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running result, complex modula- DAC tion only ...
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AD9775 0 – –40 –60 –80 –100 –8.0 –6.0 –4.0 –2.0 0 2.0 (LO (× ) OUT DATA Figure 85. 8× Interpolation, Complex f 0 –20 – ...
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FREQUENCY (MHz) Figure 91. AD9775 Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4×, Complex Modulation in AD9775 = ...
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AD9775 APPLYING THE OUTPUT CONFIGURATIONS The following sections illustrate typical output configurations for the AD9775. Unless otherwise noted assumed that IOUTFS is set to a nominal 20 mA. For applications requiring optimum dynamic performance, a differential output configu- ...
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DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to-single- ended conversion, as shown in Figure 99. This has the added benefit of providing signal gain as well. In Figure 99, the AD9775 ...
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AD9775 EVALUATION BOARD The AD9775 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from PCs running Windows® 95, Windows 98, or Windows NT®/2000. The evaluation board ...
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INPUT CLOCK AWG2021 OR DG2020 JUMPER CONFIGURATION FOR TWO-PORT MODE PLL ON SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – NOTES ...
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AD9775 INPUT CLOCK NOTES 1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1 TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED ...
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RC0603 G2 ENBL G3 VPS1 VOUT LOIP VPS2 LOIN G4A G1B G4B G1A QBBN IBBN QBBP IBBP ADTL1-12 CC0603 Figure 105. AD8345 Circuitry on AD9775 Evaluation Board Rev Page RC0603 ADTL1-12 CC0805 AD9775 ...
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AD9775 CC0603 RC0603 CC0603 RC1206 CC0603 RC0603 CC0605 Figure 106. AD9775 Clock, Power Supplies, and Output Circuitry Rev Page CC0805 ...
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Figure 107. AD9775 Evaluation Board Input (A Channel) and Clock Buffer Circuitry Rev Page AD9775 ...
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AD9775 Figure 108. AD9775 Evaluation Board Input (B Channel) and SPI Port Circuitry Rev Page ...
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Figure 109. AD9775 Evaluation Board Components, Top Side Figure 110. AD9775 Evaluation Board Components, Bottom Side Rev Page AD9775 ...
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AD9775 Figure 112. AD9775 Evaluation Board Layout, Layer Two (Ground Plane) Figure 111. AD9775 Evaluation Board Layout, Layer One (Top) Rev Page ...
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Figure 113. AD9775 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9775 Evaluation Board Layout, Layer Four (Bottom) Rev Page AD9775 ...
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... SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9775BSV −40°C to +85°C AD9775BSVRL −40°C to +85°C 1 AD9775BSVZ −40°C to +85°C 1 AD9775BSVZRL −40°C to +85°C AD9775- Pb-free part. 14.20 14. ...
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NOTES Rev Page AD9775 ...
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AD9775 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02858-0-12/06(E) Rev Page ...