AD9775BSVRL Analog Devices Inc, AD9775BSVRL Datasheet - Page 18

• Manufacturer Part Number: AD9775BSVRL
• Description: IC DAC 14BIT DUAL 160MSPS 80TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9775BSVRL

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• For Use With: AD9775-EBZ - BOARD EVALUATION FOR AD9775

MODE CONTROL (VIA SPI PORT)
Table 10. Mode Control via SPI Port
Address
0x00
0x 01
0x 02
0x 03
0x 04
0x 05
0x 06
0x 07
0x 08
0x 09
0x 0A
0x 0B
0x 0C
0x 0D
1
2
Default values are shown in bold.
See the Two-Port Data Input Mode section.
Bit 7
SDIO
Bidirectional
0 = Input
1 = I/O
Filter
Interpolation
Rate (1×, 2×,
4×, 8×)
0 = Signed
Input Data
1 = Unsigned
Data Rate
Clock Output
0 = PLL OFF
1 = PLL ON
IDAC Offset
Adjustment
Bit 9
IDAC I
Direction
0 = I
on I
1 = I
on I
QDAC Offset
Adjustment
Bit 9
QDAC I
Direction
0 = I
on I
1 = I
on I
OUTB
OUTB
OUTA
OUTA
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
2
2
Bit 6
LSB, MSB
First, 0 = MSB
1 = LSB
Filter
Interpolation
Rate (1×, 2×, 4×,
8×)
0 = Two-Port
Mode
1 = One-Port
Mode
0 = Automatic
Charge Pump
Control, 1 =
Programmable
IDAC Offset
Adjustment
Bit 8
QDAC Offset
Adjustment
Bit 8
1
Bit 5
Software
Reset on
Logic 1
Modulation
Mode
(None, f
f
DATACLK
Driver
Strength
IDAC Offset
Adjustment
Bit 7
QDAC Offset
Adjustment
Bit 7
S
/4, f
S
/8)
S
/2,
Rev. E | Page 18 of 56
Bit 4
Sleep Mode
Logic 1
Shuts Down
the DAC
Output
Currents
Modulation
Mode
(None, f
f
DATACLK
Invert
0 = No Invert
1 = Invert
IDAC Offset
Adjustment
Bit 6
QDAC Offset
Adjustment
Bit 6
S
QDAC Fine Gain Adjustment
/4, f
IDAC Fine Gain Adjustment
S
/8)
S
/2,
Bit 3
Power-Down
Mode Logic 1
Shuts Down All
Digital and
Analog
Functions
0 = No Zero
Stuffing on
Interpolation
Filters, Logic 1
Enables Zero
Stuffing.
IDAC Offset
Adjustment
Bit 5
QDAC Offset
Adjustment
Bit 5
QDAC Coarse Gain Adjustment
IDAC Coarse Gain Adjustment
Bit 2
1R/2R Mode
DAC Output
Current Set
by One or
Two External
Resistors
0 = 2R,
1 = 1R
1 = Real
Mix Mode
0 = Complex
Mix Mode
ONEPORTCLK
Invert
0 = No Invert
1 = Invert
PLL Charge
Pump
Control
IDAC Offset
Adjustment
Bit 4
QDAC Offset
Adjustment
Bit 4
Version Register
Bit 1
PLL_LOCK
Indicator
0 = e
1 = e
IQSEL Invert
0 = No Invert
1 = Invert
PLL Divide
(Prescaler)
Ratio
PLL Charge
Pump
Control
IDAC Offset
Adjustment
Bit 3
IDAC Offset
Adjustment
Bit 1
QDAC Offset
Adjustment
Bit 3
QDAC Offset
Adjustment
Bit 1
+jωt
−jωt
Bit 0
DATACLK/
PLL_LOCK
Select
0 = PLLLOCK
1 = DATACLK
Q First
0 = I First
1 = Q First
PLL Divide
(Prescaler)
Ratio
PLL Charge
Pump Control
IDAC Offset
Adjustment
Bit 2
IDAC Offset
Adjustment
Bit 0
QDAC Offset
Adjustment
Bit 2
QDAC Offset
Adjustment
Bit 0
AD9775
2