AD9775BSVRL Analog Devices Inc, AD9775BSVRL Datasheet - Page 11

• Manufacturer Part Number: AD9775BSVRL
• Description: IC DAC 14BIT DUAL 160MSPS 80TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9775BSVRL

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• For Use With: AD9775-EBZ - BOARD EVALUATION FOR AD9775

Table 9. Pin Function Descriptions
Pin No.
1, 3
2
4, 7
5
6
8
9, 17, 25, 35, 44, 52
10, 18, 26, 36, 43, 51
11 to 16, 19 to 24, 27, 28
29, 30, 49, 50
31
32
33, 34, 37 to 42, 45 to 48
53
54
55
56
57
58
59
60
61, 63, 65, 76, 78, 80
62, 64, 66, 67, 70, 71,
74, 75, 77, 79
68, 69
72, 73
Mnemonic
CLKVDD
LPF
CLKGND
CLK+
CLK−
DATACLK/PLL_LOCK
DGND
DVDD
P1B13 (MSB) to P1B0
(LSB)
NC
IQSEL/P2B13 (MSB)
ONEPORTCLK/P2B12
P2B11 to P2B0 (LSB)
SPI_SDO
SPI_SDIO
SPI_CLK
SPI_CSB
RESET
REFIO
FSADJ2
FSADJ1
AVDD
AGND
I
I
OUTB2
OUTB1
, I
, I
OUTA1
OUTA2
PLL Loop Filter.
Clock Supply Common.
Full-Scale Current Adjust, Q Channel.
Full-Scale Current Adjust, I Channel.
Description
Clock Supply Voltage.
Differential Clock Input.
Differential Clock Input.
With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1
indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved
lock. This pin may also be programmed to act as either an input or output
(Address 02h, Bit 3) DATACLK signal running at the input data rate.
Digital Common.
Digital Supply Voltage.
Port 1 Data Inputs.
No Connect.
In one-port mode, IQSEL = 1 followed by a rising edge of the differential input
clock latches the data into the I channel input register. IQSEL = 0 latches the data
into the Q channel input register. In two-port mode, this pin becomes the Port 2
MSB.
With the PLL disabled and the AD9775 in one-port mode, this pin becomes a
clock output that runs at twice the input data rate of the I and Q channels. This
allows the AD9775 to accept and demux interleaved I and Q data to the I and Q
input registers.
Port 2 Data Inputs.
In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an
output, SDO enters a High-Z state. This pin can also be used as an output for the
data rate clock. For more information, see the Two-Port Data Input Mode section.
Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 0x00.
The default setting for this bit is 0, which sets SDIO as an input.
Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output
on the SPI port is registered on the falling edge.
Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port
logic and initializes instruction cycle.
Logic 1 resets all of the SPI port registers, including Address 0x00, to their default
values. A software reset can also be done by writing a Logic 1 to SPI Register 00h,
Bit 5. However, the software reset has no effect on the bit in Address 0x00.
Reference Output, 1.2 V Nominal.
Analog Supply Voltage.
Analog Common.
Differential DAC Current Outputs, Q Channel.
Differential DAC Current Outputs, I Channel.
Rev. E | Page 11 of 56
AD9775