AD9775BSVRL Analog Devices Inc, AD9775BSVRL Datasheet - Page 20

• Manufacturer Part Number: AD9775BSVRL
• Description: IC DAC 14BIT DUAL 160MSPS 80TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9775BSVRL

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• For Use With: AD9775-EBZ - BOARD EVALUATION FOR AD9775

AD9775
ADDRESS 0x03
Bit 7: Allows the data rate clock (divided down from the DAC
clock) to be output at either the DATACLK/PLL_LOCK pin
(Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this
register enables the data rate clock at DATACLK/ PLL_LOCK,
while a 1 in this register causes the data rate clock to be output
at SPI_SDO. For more information, see the Two-Port Data
Input Mode section.
Bit 1 and Bit 0: Setting this divide ratio to a higher number
allows the VCO in the PLL to run at a high rate (for best
performance) while the DAC input and output clocks run
substantially slower. The divider ratio is set according to the
following table.
Table 13.
00
01
10
11
ADDRESS 0x04
Bit 7: Logic 0 (default) disables the internal PLL. Logic 1
enables the PLL.
Bit 6: Logic 0 (default) sets the charge pump control to
automatic. In this mode, the charge pump bias current is
controlled by the divider ratio defined in Address 0x03, Bits 1
and 0. Logic 1 allows the user to manually define the charge
pump bias current using Address 0x04, Bits 2, 1, and 0.
Adjusting the charge pump bias current allows the user to
optimize the noise/settling performance of the PLL.
Bit 2 to Bit 0: With the charge pump control set to manual,
these bits define the charge pump bias current according to the
following table.
Table 14.
000
001
010
011
111
I
I
I
OUTA
OUTB
OFFSET
=
=
=
⎡
⎢
⎢
⎣
⎡
⎢
⎢
⎣
⎛
⎜ ⎜
⎝
⎛ ×
⎜ ⎜
⎝
4
6
6
×
×
I
8
8
I
REF
I
REF
REF
⎛
⎜
⎝
⎞
⎟ ⎟
⎠
OFFSET
⎞
⎟ ⎟
⎠
⎛
⎜ ⎜
⎝
⎛
⎜ ⎜
⎝
1024
COARSE
COARSE
16
16
⎞
⎟
⎠
÷1
÷2
÷4
÷8
50 μA
100 μA
200 μA
400 μA
800 μA
(A)
+
+
1
1
⎞
⎟ ⎟
⎠
⎞
⎟ ⎟
⎠
−
−
⎛ ×
⎜ ⎜
⎝
⎛ ×
⎜ ⎜
⎝
3
3
32
32
I
I
REF
REF
⎞
⎟ ⎟
⎠
⎞
⎟ ⎟
⎠
⎛
⎜
⎝
⎛
⎜
⎝
FINE
FINE
256
256
Rev. E | Page 20 of 56
⎞
⎟
⎠
⎞
⎟
⎠
⎤
⎥
⎥
⎦
⎤
⎥
⎥
⎦
×
×
⎡
⎢
⎢
⎣
⎡
⎢
⎣
⎛
⎜
⎝
⎛
⎜
⎝
1024
1024
24
24
⎞
⎟
⎠
⎞
⎟
⎠
⎛
⎜
⎜
⎝
ADDRESS 0x05, ADDRESS 0x09
Bit 7 to Bit 0: These bits represent an 8-bit binary number
(Bit 7 MSB) that defines the fine gain adjustment of the I (0x05)
and Q (0x09) DAC, according to Equation 1.
ADDRESS 0x06, ADDRESS 0x0A
Bit 3 to Bit 0: These bits represent a 4-bit binary number (Bit 3
MSB) that defines the coarse gain adjustment of the I (0x06)
and Q (0x0A) DACs, according to Equation 1.
ADDRESS 0x07, ADDRESS 0x0B
Bit 7 to Bit 0: These bits are used in conjunction with Address
0x08, 0x0C, Bit 1 and Bit 0.
ADDRESS 0x08, ADDRESS 0x0C
Bit 1 and Bit 0: The 10 bits from these two address pairs
(0x07, 0x08 and 0x0B, 0x0C) represent a 10-bit binary number
that defines the offset adjustment of the I and Q DACs,
according to Equation 1 (0x07, 0x0B—Bit 7 MSB/0x08, 0x0C—
Bit 0 LSB).
ADDRESS 0x08, ADDRESS 0x0C
Bit 7: This bit determines the direction of the offset of the
I (0x08) and Q (0x0C) DACs. A Logic 0 applies a positive offset
current to I
to I
bits in Addresses 0x07, 0x0B, 0x08, and 0x0C, according to
Equation 1.
Equation 1 shows I
coarse gain, and offset adjustment when using the 2R mode. In
1R mode, the current I
(Pin 60). This current is divided equally into each channel so
that a scaling factor of one-half must be added to these
equations for full-scale currents for both DACs and the offset.
⎛
⎜
⎝
2
DATA
14
2
OUTB
14
−
DATA
2
. The magnitude of the offset current is defined by the
⎞
⎟
⎠
14
⎤
⎥
⎦
(A)
OUTA
−
, while a Logic 1 applies a positive offset current
1
⎞
⎟
⎟
⎠
⎤
⎥
⎥
⎦
OUTA
(A)
REF
and I
is created by a single FSADJ resistor
OUTB
as a function of fine gain,
(1)