LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 372

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
IN_DEL
ROUTE
MCLK_DEL
ROUTE
OUTREG_DEL
IN_DEL
ROUTE
MCLK_DEL
ROUTE
OUTDD_DEL
NCLK_DEL
ROUTE
Report:
From the Hold Report below, which was run for MIN conditions:
===========================================================================
Preference: CLOCK_TO_OUT PORT “ddr_cas_n” MAX 5.500000 ns CLKPORT “clk” CLKOUT PORT “ddr_clk”
;
---------------------------------------------------------------------------------------------
------------------------------------
Passed:
ddr_clk_c -)
Logical Details:
Name
Name
Name
Name
Source:
Destination:
•
Data path ddr_cas_n to ddr_cas_n:
Clock out path:
Feedback path:
t
DDR_CLK
The following path meets requirements by 1.056ns
Fanout
Fanout
Fanout
Fanout
2.318ns is the minimum offset for this preference.
---
---
449
---
---
---
449
---
---
136
1 item scored, 0 timing errors detected.
(min) = 3.043 - 1.905 = 1.138 ns
1
1
--------
--------
--------
--------
Unknown
Cell type
Port
Delay (ns)
1.431
0.816
0.385
3.714
6.346
Delay (ns)
1.713
1.713
Delay (ns)
1.431
0.816
0.385
1.191
1.918
5.741
Delay (ns)
0.385
2.886
3.271
LLHPPLL.CLKIN to
LLHPPLL.CLKIN to
LLHPPLL.CLKIN to
LLHPPLL.MCLK to
(28.6% logic, 71.4% route), 2 logic levels.
(100.0% logic, 0.0% route), 1 logic levels.
LLHPPLL.MCLK to
(65.0% logic, 35.0% route), 3 logic levels.
LLHPPLL.NCLK to
(11.8% logic, 88.2% route), 1 logic levels.
Q
Pin type
Pad
AF3.OUTDD to
AB4.INCK to
AB4.INCK to
AB4.PAD to
AE15.SC to
AB4.PAD to
Site
Site
Site
Site
18-12
U1_ddrct_np_o4_1_008/U1_cmdexe/ddr_cas_nZ0
LLHPPLL.CLKIN clk_c
LLHPPLL.CLKIN clk_c
Cell name
ddr_cas_n
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
AF3.OUTDD ddr_clk_c
AB4.INCK clk
AE15.PAD ddr_cas_n (from ddr_clk_c)
AB4.INCK clk
AE15.SC ddr_clk_c
AF3.PAD ddr_clk
for the DDR SDRAM Controller IP Core
(clock net +/-)
Resource
Resource
Resource
Resource
Board Timing Guidelines
(from