LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 341

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
registers in the design are asynchronously set or reset by the same wire. The following examples show the correct
syntax for instantiating GSR in the VHDL and Verilog codes.
Use PIC Features
Using I/O Registers/Latches in PIC
Moving registers or latches into Input/Output cells (PIC) may reduce the number of PFUs used and decrease rout-
ing congestion. In addition, it reduces setup time requirements for incoming data and clock-to-output delay for out-
put data, as shown in Figure 13-11. Most synthesis tools will infer input registers or output registers in PIC if
possible. Users can set synthesis attributes in the specific tools to turn off the auto-infer capability. Users can also
instantiate library elements to control the implementation of PIC resource usage.
Figure 13-11. Moving FF into PIC Input Register
Figure 13-12. Moving FF into PIC Output Register
-- VHDL Example of GSR Instantiation
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gsr_test is
end gsr_test;
architecture behave of gsr_test is
begin
end behave;
port (rst, clk: in std_logic;
cntout : out std_logic_vector(1 downto 0));
signal cnt : std_logic_vector(1 downto 0);
u1: GSR port map (gsr=>rst);
process(clk, rst)
begin
end process;
cntout <= cnt;
IN_SIG
D
PFU
Before Using Output Register
Before Using Input Register
Q
if rst = '1' then
elsif rising_edge (clk) then
end if;
PIC
cnt <= "00";
cnt <= cnt + 1;
PIC
OUT_SIG
D
PFU
Q
13-14
// Verilog Example of GSR Instantiation
module gsr_test(clk, rst, cntout);
input clk, rst;
output[1:0] cntout;
reg[1:0] cnt;
GSR u1 (.GSR(rst));
always @(posedge clk or negedge rst)
begin
end
assign cntout = cnt;
endmodule
if (!rst)
else
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
After Using Output Register
cnt = 2'b0;
cnt = cnt + 1;
After Using Input Register
IN_SIG
D
Q
PIC
PIC
OUT_SIG
D
Q