LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 158

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Verilog for Synplify
This section lists syntax and examples for all the sysIO Attributes in Verilog using the Synplify synthesis tool.
Syntax
Table 8-9. Verilog Synplify Attribute Syntax
Examples
//IO_TYPE, PULLMODE, SLEWRATE and DRIVE assignment
output portB /*synthesis IO_TYPE="LVCMOS33" PULLMODE =”UP” SLEWRATE =”FAST”
DRIVE =”20”*/;
output portC /*synthesis IO_TYPE="LVDS25" */;
//OPENDRAIN
output portA /*synthesis OPENDRAIN =”ON”*/;
//PCICLAMP
output portA /*synthesis IO_TYPE="PCI33" PULLMODE =”PCICLAMP”*/;
// Fixeddelay
input load /* synthesis FIXEDDELAY="TRUE" */;
// Place the flip-flops near the load input
input load /* synthesis din=”” */;
// Place the flip-flops near the outload output
output outload /* synthesis dout=”” */;
IO_TYPE
OPENDRAIN
DRIVE
PULLMODE
PCICLAMP
SLEWRATE
FIXEDDELAY
DIN
DOUT
LOC
Attribute
PinType PinName /* synthesis IO_TYPE=”IO_Type Value”*/;
PinType PinName /* synthesis OPENDRAIN =”OpenDrain Value”*/;
PinType PinName /* synthesis DRIVE=”Drive Value”*/;
PinType PinName /* synthesis PULLMODE=”Pullmode Value”*/;
PinType PinName /* synthesis PCICLAMP =” PCIClamp Value”*/;
PinType PinName /* synthesis SLEWRATE=”Slewrate Value”*/;
PinType PinName /* synthesis FIXEDDELAY=”Fixeddelay Value”*/;
PinType PinName /* synthesis DIN=” “*/;
PinType PinName /* synthesis DOUT=” “*/;
PinType PinName /* synthesis LOC=”pin_locations “*/;
8-18
Syntax
LatticeECP/EC and LatticeXP
sysIO Usage Guide