LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 191

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Figure 9-28. ROM Primitive for LatticeECP/EC and LatticeXP Devices
In the ROM mode the address for the port is registered at the input of the memory array. The output data of the
memory is optionally registered at the output.
The various ports and their definitions for the ROM are included in Table 9-10. The table lists the corresponding
ports for the module generated by IPexpress and for the ROM primitive.
Table 9-10. EBR-based ROM Port Definitions
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit
bus, so it can cascade eight memories easily. However, if the memory size specified by the user requires more than
eight EBR blocks, the software automatically generates the additional address decoding logic, which is imple-
mented in the PFU (external to the EBR blocks).
While generating the ROM using IPexpress, the user is required to provide an initialization file to pre-initialize the
contents of the ROM. These file are the *.mem files and they can be of Binary, Hex or the Addressed Hex formats.
The initialization files are discussed in detail in the Initializing Memory section of this technical note.
Users have the option of enabling the output registers for Read Only Memory (ROM). Figures 8-27 and 8-28 show
the internal timing waveforms for the Read Only Memory (ROM) with these options.
Address
OutClock
OutClockEn
Reset
—
Port Name in generated
Module
AD[x:0]
CLK
CE
RST
CS[2:0]
CS[2:0]
AD[x:0]
Port Name in the EBR
RST
CLK
CE
block primitive
9-26
EBR
Read Address
Clock
Clock Enable
Reset
Chip Select
Description
LatticeECP/EC and LatticeXP Devices
DO[y:0]
—
Rising Clock Edge
Active High
Active High
—
Memory Usage Guide
Active State