LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 342

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Inferring Bi-directional I/O
Users can either structurally instantiate the bi-directional I/O library elements, or behaviorally describe the I/O
paths to infer bi-directional buffers. The following VHDL and Verilog examples show how to infer bi-directional I/O
buffers.
Specifying I/O Types and Locations
Users can either assign I/O types and unique I/O locations in the Preference Editor or specify them as attributes in
the VHDL or Verilog source code. The following examples show how to add attributes in the Synplify and Leonardo-
Spectrum synthesis tool sets. For a complete list of supported attributes, refer to the HDL Attributes section of the
ispLEVER on-line help system.
-- VHDL example of specifying I/O type and location attributes for Synplify & Leonardo
-- Verilog example of specifying I/O type and location attributes for Synplify & Leonardo
entity cnt is
end entity cnt;
module cnt(clk,res);
endmodule
-- Inferring Bi-directional I/O in VHDL
library ieee;
use ieee.std_logic_1164.all;
entity bidir_infer is
end bidir_infer;
architecture lattice_fpga of bidir_infer is
begin
end lattice_fpga
port(A, B
B <= A when (dir='1') else 'Z';
A <= B when (dir='0') else 'Z';
port(clk: in std_logic;
attribute LEVELMODE: string:
attribute LEVELMODE of clk : signal is “SSTL2”;
attribute LOC of clk : signal is “V2”;
attribute LEVELMODE of res : signal is “SSTL2”;
attribute LOC of res : signal is “V3”;
input clk /* synthesis LEVELMODE=”SSTL2” LOC=”V2”*/;
output res /* synthesis LEVELMODE=”SSTL2” LOC=”V3” */;
...
// exemplar begin
// exemplar end
dir
// exemplar attribute clk LEVELMODE SSTL2
// exemplar attribute clk LOC V2
// exemplar attribute res LEVELMODE SSTL2
// exemplar attribute res LOC V3
res: out std_logic);
: inout std_logic;
: in std_logic);
13-15
// Inferring Bi-directional I/O in Verilog
module bidir_infer (A, B, DIR);
inout A, B;
input DIR;
assign B = (DIR)
assign A = (~DIR) ? B : 1'bz;
endmodule
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
? A : 1'bz;