LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 271

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Table 11-6. DCS Attributes
Figure 11-12. DCS Primitive Symbol
DCS Waveforms
The DCSOUT waveform timing is described in Figure 11-13 for each mode. The ‘POS’ and ‘NEG’ modes describe
DCSOUT timing at both the falling and rising edges of SEL.
Figure 11-13. DCS Waveforms
DCS MODE = POS
At the rising edge (POS) of SEL, the DCSOUT changes from CLK0 to CLK1. This mode is the default mode.
DCS MODE
Attribute Name
DCSOUT
CLK1
SEL
CLK0
SEL Falling edge:
- Wait for CLK1 rising edge,
- Switch output at CLK0 rising edge
latch output & remain high
Rising edge triggered, latched state is high
Falling edge triggered, latched state is low
Sel is active high, Disabled output is low
Sel is active high, Disabled output is high
Sel is active low, Disabled output is low
Sel is active low, Disabled output is high
Buffer for CLK0
Buffer for CLK1
Description
DCS MODE = POS
CLK0
CLK1
SEL
11-15
DCS
DCSOUT
sysCLOCK PLL Design and Usage Guide
SEL=0
SEL Rising edge:
- Wait for CLK0 rising edge,
- Switch output at CLK1 rising edge
CLK0
CLK0
CLK0
CLK0
CLK0
CLK1
latch output & remain high
0
1
Output
LatticeECP/EC and LatticeXP
SEL=1
CLK1
CLK1
CLK1
CLK1
CLK0
CLK1
0
1
POS (Default)
HIGH_HIGH
HIGH_LOW
LOW_HIGH
LOW_LOW
Value
CLK0
CLK1
NEG