LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 326

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Lattice ispTRACY Usage Guide
Figure 14-10. ispLA Project Setup Window - Event Pattern Setup
The Event Pattern window configures the patterns for EV0 and EV1. Pattern 0 corresponds to EV0 and Pattern 1
corresponds to EV1. The sample types for trigger signals depends on whether the signal is edge or level sensitive.
If the signal is level sensitive, in the middle pattern window, only logic 0 (0) ,logic (1) or don't care (X) are available.
For edge sensitive signals, the options are logic 0 (0), logic 1 (1), rising (R), falling (F), both/either edge (B) or don't
care (X). In this window, changes to the pattern are made in the center section (Pattern 1 or Pattern 0) and the
changes are reflected in the right section.
To begin sampling , click on the green run button. Sampling will complete when the trigger conditions are met. The
data will be uploaded through the JTAG cable and results displayed I the Signal Analysis window. Figure 14-11
shows the Signal Analysis window after a data capture cycle.
Figure 14-11. ispLA Signal Analysis Window
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