LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 237

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Some reference documents that discuss board layout guidelines:
References
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet: www.latticesemi.com
Revision History
• www.idt.com, IDT, PCB Design for Double Data Rate Memory.
• www.motorola.com, AN2582, Hardware and Layout Design Considerations for DDR Interfaces.
• www.micron.com, TN4607, DDR 333 Design Guide for Two DIMM Systems
• www.jedec.org – JEDEC Standard 79, Double Data Rate (DDR) SDRAM Specification
• www.micron.com – DDR SDRAM Data Sheets
• www.infinion.com – DDR SDRAM Data Sheets
• www.samsung.com – DDR SDRAM Data Sheets
• www.latticesemi.com – RD1019 QDR Memory Controller Reference Design for LatticeECP/EC devices
• www.toshiba.com – DDR FCRAM Data Sheet
• www.fujitsu.com – DDR FCRAM Data Sheet
• www.latticesemi.com – LatticeEC Advanced Evaluation Board User’s Guide
• www.latticesemi.com – DDR SDRAM Controller (Pipelined Version for LatticeECP/EC Devices) User's
February 2007
Guide
[phone] (Outside North America)
[e-mail]
Date
—
Version
03.2
—
Previous Lattice releases.
Updated Generic High Speed DDR Implementation section.
Updated Appendix D.
10-18
Change Summary
LatticeECP/EC and LatticeXP
DDR Usage Guide