LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 355

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Figure 17-8. PAR Options Window
Figure 17-9. Example PAR report (.par) File, Routing Section
The place and route (.par) report file contains execution information about the PAR command run. The report also
shows the steps taken as the program converges on a placement and routing solution. In the routing convergence
example text in Figure 17-9, the number in parenthesis is the timing score after each iteration. In this example, tim-
ing was met after three routing iterations, as can be seen from the (0) timing score.
Using Multiple Placement Iterations (Cost Tables)
Using multiple placement iterations can be achieved by selecting the Advanced Options in Figure 17-8.
As shown in the Advanced Options of Figure 17-8, the number of iterations is set to 10 and the placement start
point is set to iteration 1 (cost table 1). Only the best NCD file is to be saved as per the following line. Once PAR
runs, the tool will loop back through the place and route flow until the number of iterations has reached 10. In this
0 connections routed; 26590 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 11 mins 31 secs
Starting iterative routing.
End of iteration 1
26590 successful; 0 unrouted; (151840) real time: 14 mins 29 secs
Dumping design to file
d:\ip\design.ncd.
End of iteration 2
26590 successful; 0 unrouted; (577) real time: 16 mins 23 secs
Dumping design to file
d:\ip\design.ncd.
End of iteration 3
26590 successful; 0 unrouted; (0) real time: 17 mins 39 secs
Dumping design to file
17-11
Lattice Semiconductor FPGA
Successful Place and Route