KSZ8851SNLI Micrel Inc, KSZ8851SNLI Datasheet - Page 58

• Manufacturer Part Number: KSZ8851SNLI
• Manufacturer: Micrel Inc

Specifications of KSZ8851SNLI

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0
The 64-bit MAC address table is used for group address filtering and it is enabled by selecting item 5 “Hash perfect” mode
in Table 3 (Address Filtering Scheme). This value is defined as the six most significant bits from CRC circuit calculation
result that is based on 48-bit of DA input. The two most significant bits select one of the four registers to be used, while
the others determine which bit within the register.
Multicast table register 0.
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1
Multicast table register 1.
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2
Multicast table register 2.
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3
Multicast table register 3.
0xA8 – 0xAF: Reserved
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR
This register is used to control the flow control for low watermark in QMU RX queue.
August 2009
Micrel, Inc.
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-12
11-0
-
Default Value
0x0
Default Value
0x0
Default Value
0x0
Default Value
0x0
Default Value
0x0500
R/W
RW
R/W
RW
R/W
RW
R/W
RW
R/W
RW
RW
Description
HT0 Hash Table 0
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Description
HT1 Hash Table 1
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1,
all multicast addresses are received regardless of the multicast table value.
Description
HT2 Hash Table 2
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1,
all multicast addresses are received regardless of the multicast table value.
Description
HT3 Hash Table 3
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1,
all multicast addresses are received regardless of the multicast table value.
Description
Reserved
FCLWC Flow Control Low Watermark Configuration
These bits are used to define the QMU RX queue low watermark configuration. It is in
double words count and default is 5.12 KByte available buffer space out of 12 KByte.
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KSZ8851SNL/SNLI
M9999-083109-2.0