KSZ8851SNLI Micrel Inc, KSZ8851SNLI Datasheet - Page 24

• Manufacturer Part Number: KSZ8851SNLI
• Manufacturer: Micrel Inc

Specifications of KSZ8851SNLI

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

0 contains only opcode (10: read command, 11: write command) and the following is read/write data phase.
Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has
built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each
queue contains 12KB for RXQ and 6KB for TXQ of memory with back-to-back, non-blocking frame transfer performance.
It provides a group of control registers for system control, frame status registers for current packet transmit/receive status,
and interrupts to inform the host of the real time TX/RX status.
Transmit Queue (TXQ) Frame Format
The frame format for the transmit queue is shown in the following Table 6. The first word contains the control information
August 2009
Micrel, Inc.
SCLK
SCLK
CSN
CSN
SO
SO
SI
SI
D7
X
D6
X
1
Read Data Byte 3
RXQ Read Command Byte 0
D5
X
0
High Impedance
D4
X
X
D3
X
X
D2
X
X
D1
X
X
D0
X
X
Figure 10. TXQ FIFO Write Timing
Figure 9. RXQ FIFO Read Timing
D7
X
X
D6
D7
X
X
Read Data Byte 4
D5
D6
X
X
Read Data Byte 1
D4
D5
X
X
D3
X
D4
X
24
D2
X
D3
X
D1
X
D2
X
D0
X
D1
X
X
D0
D7
X
D7
X
D6
X
Read Data Byte 2
D6
X
Read Data Byte N
D5
X
D5
X
D4
X
D4
X
D3
X
D3
X
KSZ8851SNL/SNLI
D2
X
D2
X
M9999-083109-2.0
D1
X
D1
X
D0
X
D0
X