KSZ8851SNLI Micrel Inc, KSZ8851SNLI Datasheet - Page 57

• Manufacturer Part Number: KSZ8851SNLI
• Manufacturer: Micrel Inc

Specifications of KSZ8851SNLI

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

0x94 – 0x9B: Reserved
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR
This register indicates the current total amount of received frame count in RXQ frame buffer and also is used to program
the received frame count threshold.
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR
This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.
August 2009
Micrel, Inc.
Bit
6
5
4
3
2
1
0
Bit
15-8
7-0
Bit
15-0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default Value
Default Value
0x00
0x00
Default Value
0x0000
R/W
RO
(W1C)
RO
RO
RO
RO
RO
(W1C)
RO
R/W
RO
RW
R/W
RW
Description
RXFC RX Frame Count
To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1
in ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read
the updated receive frame header information in RXFHSR/RXFHBCR registers after read
this RX frame count register.
RXFCT Receive Frame Count Threshold
To program received frame count threshold value.
When bit 5 set to 1 in RXQCR register, the KSZ8851SNL will set RX interrupt (bit 13 in
ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this
register.
Description
TXNTFS TX Next Total Frames Size
The host CPU is used to program the total amount of TXQ buffer space which is required
for next total transmit frames size in double-word count.
When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the
KSZ8851SNL will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is
available based upon the total amount of TXQ space requested by CPU at this register.
Description
TXSAIS Transmit Space Available Interrupt Status
When this bit is set, it indicates that Transmit memory space available status has
occurred.
When this bit is reset, the Transmit memory space available interrupt is disabled.
RXWFDIS Receive Wakeup Frame Detect Interrupt Status
When this bit is set, it indicates that Receive wakeup frame detect status has occurred.
Write “1000” to PMECR[5:2] to clear this bit
RXMPDIS Receive Magic Packet Detect Interrupt Status
When this bit is set, it indicates that Receive magic packet detect status has occurred.
Write “0100” to PMECR[5:2] to clear this bit.
LDIS Linkup Detect Interrupt Status
When this bit is set, it indicates that wake-up from linkup detect status has occurred.
Write “0010” to PMECR[5:2] to clear this bit.
EDIS Energy Detect Interrupt Status
When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up from
energy detect status has occurred. When this bit is set and bit 2, 0=1 in IER register, it
indicates that wake-up from delay energy detect status has occurred.
Write “0001” to PMECR[5:2] to clear this bit.
SPIBEIS SPI Bus Error Interrupt Status
When this bit is set, it indicates that SPI bus error status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
57
KSZ8851SNL/SNLI
M9999-083109-2.0