KSZ8851SNLI Micrel Inc, KSZ8851SNLI Datasheet - Page 48

• Manufacturer Part Number: KSZ8851SNLI
• Manufacturer: Micrel Inc

Specifications of KSZ8851SNLI

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3
This register contains the last 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 3. Setting bit 15 selects the 64th byte of the Wake up frame 3.
0x6C – 0x6F: Reserved
Transmit Control Register (0x70 – 0x71): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Transmit Status Register (0x72 – 0x73): TXSR
This register keeps the status of the last transmitted frame.
August 2009
Micrel, Inc.
Bit
15-0
Bit
15-9
8
7
6
5
4
3
2
1
0
-
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default Value
0
Default Value
R/W
RW
R/W
RO
RW
RO
RW
RW
RW
RW
RW
RW
RW
Description
WF3BM3
Wake up Frame 3 Byte Mask 3. The last 16 bytes mask covering bytes 49 to 64 of a
Wake up frame 3 pattern.
Description
Reserved
TCGICMP Transmit Checksum Generation for ICMP
When this bit is set, The KSZ8851SNL is enabled to transmit ICMP frame (only for non-
fragment frame) checksum generation.
Reserved
TCGTCP Transmit Checksum Generation for TCP
When this bit is set, The KSZ8851SNL is enabled to transmit TCP frame checksum
generation.
TCGIP Transmit Checksum Generation for IP
When this bit is set, The KSZ8851SNL is enabled to transmit IP header checksum
generation.
FTXQ Flush Transmit Queue
When this bit is set, The transmit queue memory is cleared and TX frame pointer is reset.
Note: Disable the TXE transmit enable bit[0] first before set this bit, then clear this bit to
normal operation.
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8851SNL is in full-duplex mode, flow control is enabled.
The KSZ8851SNL transmits a PAUSE frame when the Receive Buffer capacity reaches a
threshold level that will cause the buffer to overflow.
When this bit is set and the KSZ8851SNL is in half-duplex mode, back-pressure flow
control is enabled. When this bit is cleared, no transmit flow control is enabled.
TXPE Transmit Padding Enable
When this bit is set, the KSZ8851SNL automatically adds a padding field to a packet
shorter than 64 bytes.
Note: Setting this bit requires enabling the add CRC feature (bit1=1) to avoid CRC errors
for the transmit packet.
TXCE Transmit CRC Enable
When this bit is set, the KSZ8851SNL automatically adds a 32-bit CRC checksum field to
the end of a transmit frame.
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state. When
reset, the transmit process is placed in the stopped state after the transmission of the
current frame is completed.
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KSZ8851SNL/SNLI
M9999-083109-2.0